MIMXRT1021CAF4B. External ethernet reference clock.

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

MIMXRT1021CAF4B. External ethernet reference clock.

439 Views
Haliaeetus
Contributor I

Hello,

I have a few questions about MAC configuration in MIMXRT1021CAF4B.

Hardware setup:
Physical interface (lan8742a) connected to MAC through RMII. PHY has 25MHz oscillator connected and It generates 50MHz reference clock signal for MAC. PHY is capable of working at 10 Mbps or 100Mbps (pin configuration of PHY).

Software:
I'm using evkmimxrt1020_enet_rxtx_transfer example from sdk. I have changed phy driver, and pins configuration to match custom pcb. 

Current state:
PHY successfully links to MAC after auto-negotiation. As designed in sdk, application sends twenty broadcast frames and then listens. The problem is that MAC is unable to receive any frame including broadcast. I've checked receive buffers in RAM and it is always filled with zeros. Also, I've enabled statistic registers and twenty frames sent are counted as transmitted correctly but there is no frame counted as received, even incorrectly because of invalid CRC etc.

My questions are:
1. Should I configure any additional enet reference clock's registers ?
I've checked ENET_REF_CLK_DIR bit of IOMUXC_GPR_GPR1 register during runtime and it is set to zero (ENET_REF_CLK is input) and MUX_MODE bits of SW_MUX_CTL_PAD_GPIO_AD_B0_08 register and it is set to 100 (pin b0_08 configured as ENET_REF_CLK1).

2.1 Is it a problem that this version of package is capable to work at maximum of 400MHz ?
In the example (which is designed for evaluation board with MIMXRT1021DAF5A capable to work at maximum of 500MHz) there is a comment in code:

void BOARD_InitModuleClock(void)
{
/* Set 50MHz output clock required by PHY. The 500MHz is for core rather than ethernet. */
const clock_enet_pll_config_t config = {.enableClkOutput = true, .enableClkOutput500M = true, .loopDivider = 1};
CLOCK_InitEnetPll(&config);

/* Output 50MHz clock to PHY. */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
}

(In custom version true in IOMUXC_EnableMode is changed to false to set ref_clk as input, I'm not sure about PLL part).

2.2 Should that PLL enet clock be enabled at all, if reference clock is external ? 

Thank you for your time.

Labels (1)
0 Kudos
1 Reply

397 Views
Omar_Anguiano
NXP TechSupport
NXP TechSupport

Hello
Hope you are well.

1) No, it is enough to configure the pin and the direction.

2) Yes, this limitation is for the core clock. By default, the Enet PLL generates the core clock so to comply the industrial grade limitation it is needed to use another PLL for core clock. I suggest you leave this PLL enabled and use System PLL for core clock and configure it to operate below 400Mhz.

You can use config tools to configure this.

Best regards,
Omar

0 Kudos