Location of flexspi NOR configuration parameters...

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Location of flexspi NOR configuration parameters...

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EdSutter
Senior Contributor II

I've been working with iMXRT1062 in various forms (EVK, Teensy4.1 and custom HW) for a while, and I am currently wrestling with a bootup issue (see this post).  For the sake of this question, just assume I am booting the MIMXRT1060-EVK...

I have a boot image that is derived from the examples.  The final .elf file shows me that the location of the flash config parameters (defined in the SDK file 'evkmimxrt1060_flexspi_nor_config.c') are at the base of the QuadSPI device's memory space (0x60000000).  This has been working on multiple boards for months.

Now that I'm digging into a boot problem (using a larger boot device), I read something that I didn't notice until now...

Section 9.6.1.2 "FlexSPI Serial NOR Flash Boot Operation" of the reference manual says:

The ROM expects the 512-byte FlexSPI NOR configuration parameters (as explained
in the next section) to be present at offset 0x400 in Serial NOR flash attached to FLEXSPI_A_SS0_B.

My empirical data tells me this 0x400 offset is wrong simply because I've been booting my boards with this data at 0x000 offset for quite some time.  Am I just confused and lucky, or is the text in the reference manual wrong?

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mjbcswitzerland
Specialist V

Hi

The i.MX RT 1011 has its configuration parameters located at 0x400 but I never saw anyone set up other parts for this address - invariably 0x0 offset is used.

Possibly the i.MX RT 106x probes 0x400 first and, when it doesn't find the expected signature there, tries at 0x0 (?)

I have also worked on 12 different (non-i.MX RT 1011) HW designs which have always been happy with 0x0 offset so would not place too much weight o the line in the document.

Regards

Mark

 

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mjbcswitzerland
Specialist V

Hi

The i.MX RT 1011 has its configuration parameters located at 0x400 but I never saw anyone set up other parts for this address - invariably 0x0 offset is used.

Possibly the i.MX RT 106x probes 0x400 first and, when it doesn't find the expected signature there, tries at 0x0 (?)

I have also worked on 12 different (non-i.MX RT 1011) HW designs which have always been happy with 0x0 offset so would not place too much weight o the line in the document.

Regards

Mark

 

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EdSutter
Senior Contributor II

Thanks Mark,

Yea, you know what I'm dealing with regarding the boot of the '01G device (still not resolved), so these small details should be picked up by NXP to update the documentation or explain it so that we don't have to speculate on what the real details are.

Anyone from NXP listening??

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