IMXRT1060 DCDC_PSWITCH behavior

cancel
Showing results for 
Search instead for 
Did you mean: 

IMXRT1060 DCDC_PSWITCH behavior

Jump to solution
248 Views
spencev
Contributor II

I am driving DCDC_PSWITCH HIGH to turn on the DCDC converter but I do not see any documentation beyond that. What happens if I drive DCDC_PSWITCH low after it has been HIGH? Can I use this to shutdown the cpu if the voltage drops below a certain voltage and start it back up when it is stable again? Is this safe?

I have experimented with driving it LOW and it seems to reset the processor back to the state when it is waiting for DCDC_PSWITCH to go HIGH. I am then able to drive it HIGH to start everything back up. I am just wondering if this is intended behavior and what exactly is happening when I do this?

Labels (1)
0 Kudos
1 Solution
190 Views
gusarambula
NXP TechSupport
NXP TechSupport

Hello Spencev,

I see how your DCDC_PSWITCH would make sense in theory, and as you tested it may work. However, this is not the intended usage of the DCDC_PSWITCH signal so robust operation cannot be guaranteed as this configuration has not been validated.

The recommendations on how to setup the i.MXRT1060 are available on the Hardware Development Guide for the i.MXRT1060 (link below, please note that you may need to login to download this document).

https://www.nxp.com/webapp/Download?colCode=MIMXRT105060HDUG

Regards,
Gustavo

View solution in original post

7 Replies
214 Views
spencev
Contributor II

Hello,

Thanks for some clarification on the topic. One detail I failed to provide is that my current plan is to leave POR_B disconnected and allow the internal POR_B to take over. In this case can I toggle DCDC_PSWITCH without issues and allow the internal POR_B to toggle itself accordingly?

In my testing everything seems to work just fine, I'm essentially able to use DCDC_PSWITCH as a reset (Without needing an external POR_B), but I am doing so without knowing how the internal POR_B is behaving. My guess was that once DCDC_PSWITCH goes LOW, internal POR_B no longer meets the requirement of VDD_SOC_IN being high and goes low. Then it will wait for the requirement to be met again which it should after DCDC_PSWITCH goes HIGH again. This is just a theory as I am unable to verify this with any documentation or access to internal POR_B.

If this is not recommended I will have to find another way around my limitation of pins to drive DCDC_PSWITCH and POR_B.

0 Kudos
204 Views
mjbcswitzerland
Specialist V

Hi

If you leave POR_B disconnected or pulled high the internal POR signal will take over (AND'ed).

mjbcswitzerland_0-1628428594446.png

According to the description it will follow the VCC_SOC_IN supply and delay negation by 1ms, which means that you can probably do what you are doing and use the DCDC_PSWITCH input to control the power and also reset.

This is however something that I haven't done and so have no practical experience on its overall reliability. My technique has always to be in control of the details and also the overall power supply cycling so that recovery from any latch-up situations (particularly related with initial silicon), ISP and debugger control can be ensured.

Regards

Mark

 

191 Views
gusarambula
NXP TechSupport
NXP TechSupport

Hello Spencev,

I see how your DCDC_PSWITCH would make sense in theory, and as you tested it may work. However, this is not the intended usage of the DCDC_PSWITCH signal so robust operation cannot be guaranteed as this configuration has not been validated.

The recommendations on how to setup the i.MXRT1060 are available on the Hardware Development Guide for the i.MXRT1060 (link below, please note that you may need to login to download this document).

https://www.nxp.com/webapp/Download?colCode=MIMXRT105060HDUG

Regards,
Gustavo

View solution in original post

184 Views
spencev
Contributor II

@mjbcswitzerland  Thanks for the clarification, that is how I was understanding this as well.

 

@gusarambula 

Thanks,

So DCDC_PSWITCH is strictly used to turn on the DCDC converter once and stay HIGH indefinitely? Do I need to monitor the voltage after initially setting DCDC_PSWITCH HIGH or do I set it HIGH and forget it? I am curious as to what exactly setting this LOW is doing if it is not intended.

I will try and find a way to add POR_B to my design for resetting if there is not such a way without it.

0 Kudos
178 Views
gusarambula
NXP TechSupport
NXP TechSupport

Hello Spencev,

That is correct. In the recommended configuration DCDC_PSWITCH would be asserted with a delay of at least 1ms after DCDC_IN is stable and then stay HIGH during operation. You may just set it to HIGH and forget it.

You may use the internal POR_B control as Mark already mentioned if you do not need a reset signal. Alternatively, there is a NMI (non-maskable interrupt) signal that may serve in some ways similarly to a reset signal).

My apologies for the inconvenience.

Regards,
Gustavo

173 Views
spencev
Contributor II

Thanks again for clarifying and no worries, I am working with a small number of pins to control these signals (due to space constraints) and it is forcing me to come up with creative solutions. I believe I have a solution that should be much better in the end with no compromises or unintended use of pins!

0 Kudos
229 Views
mjbcswitzerland
Specialist V

Hi

The DCDC_PSWITCH input enables/disables the internal DC/DC converter that generates the 1.1V for the VDD_SOC_IN and it is advised to also set the processor's reset input (POR) to '0' when this is not ready - thus, if powering down this voltage by using the DCDC_PSWITCH, it is also advised to hold the processor in reset (POR) while it is powered down and until it has powered up again - meaning that POR should stay low for about 10ms after DCDC_PSWITCH has been taken high (again) to ensure it has stabilised.

For users of A revision silicon (although I believe it is only critical for 105x parts), more attention has to be paid to power cycling due to a few HW erratas that can stop the DCDC converter starting and inrush current on GPIOs when the 1.1V is not available that can - in the worst case - damage the device.

This is the timing for 105x parts with errata workaround as reference, whereby the complete sequence should be repeated when powering down the internal DCDC converter.

mjbcswitzerland_0-1628329197816.png

Chip solution: https://www.utasker.com/docs/iMX/uTasker_iMX_WDOG.pdf

Regards

Mark