IMX RT1060 - pin slew rate issue

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IMX RT1060 - pin slew rate issue

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vincent_rocu
Contributor I

Hello,

I'm starting to use the board IMX RT1060-EVK And I meet the following issue :

I tried to implement a SPI bus on the "arduino header" of the board, but I have a very bad slew-rate on the pin (rising/falling edge duration are around 10µs, so a max bus frequency of 50kHz...).

I tried without success many different config for the corresponding IOMUXC_SW_PAD_CTL_PAD_xxx register of the concerned pin (no impact in case of change in the field SPEED, DSE or SRE, even with a config value 0x10B0 as shown in many examples).

I had no more success when trying to drive directly the pin in GPIO mode.

Has anyone met such an issue with this board?

Best regards,

Vincent.

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jeremyzhou
NXP Employee
NXP Employee

Hi Vincent,

Thanks for your reply.
I use two MIMXRT1060 boards for testing, one acts the master role, another is the slave, and the boards are set as below.
==============
Weld 0Ω resistor to R278,R279,R280,R281.

SPI one board:
Transfer data from one board instance to another board's instance.
SPI0 pins are connected with SPI0 pins of another board
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
INSTANCE0(SPI0)     CONNECTS TO         INSTANCE0(SPI0)
Pin Name   Board Location     Pin Name  Board Location
SOUT        J24 pin 4           SIN       J24 pin 5
SIN         J24 pin 5           SOUT      J24 pin 4
SCK         J24 pin 6           SCK       J24 pin 6
PCS0        J24 pin 3           PCS0      J24 pin 3
GND         J24 pin 7           GND       J24 pin 7
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Note: int_b2b_transfer demos is from the SDK_2.6.2_EVK-MIMXRT1060.

Have a great day.

TIC

 

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vincent_rocu
Contributor I

Hello Jeremy,

Thanks for your answer.

Concerning the sw, I confirm you that I use the API shown in the sample SDK as shown below :

void LPSPI1_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */

IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_SD_B0_00 is configured as LPSPI1_SCK */
0U); /* Software Input On Field: Input Path is determined by functionality */

...

IOMUXC_SetPinConfig(
IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_SD_B0_00 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate

...

}

Concerning the pin config, I confirm that I tested different configuration to try the different options offered for the pad setting (DSE / slew rate ...) and I obtained the result below (C1 channel=SPI_CLK, C2 channel=SPI_CS)

pastedImage_1.png

I also tested the following pin config without success :

- 0x28 (DSE=R0/5, minimum slew rate/speed),

- 0xe9 (DSE=R0/5, speed/slew rate)

- 0x1028 (DSE=R0/5, minimum slew rate/speed + keeper enabled)

- 0x10e9 (DSE=R0/5, maximum slew rate/speed + keeper enabled)

I tested the default config (API with 0x10b0 config) on a RT1050-EVKB board, and I got a correct behaviour of the SPI pin.

Do you have any idea of what could be the problem?

Thank you.

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jeremyzhou
NXP Employee
NXP Employee

Hi Vincent,

Thanks for your reply.
Actually, I'm a bit confused, whether you mean the LPSPI demo in the RT1060's SDK library doesn't work as expected, and what the mean of 'I got a correct behavior of the SPI pin', I was wondering if you can demonstrate its 'correct behavior of the SPI pin'.
Looking forward to your reply.

Have a great day.

TIC

 

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vincent_rocu
Contributor I

Hello,

Thanks for your feedback, here are some clarifications :

Below are two pictures the "correct behaviour" of the LPSPI1 on the 1050 kit (in red the MOSI line, in yellow, the CLK).

We see on the second picture (a zoom view of the same SPI transaction shown in picture 1) that the slew rate of the pin is around 5ns, instead of the 10µs measured on the 1060 kit.

pastedImage_1.png

pastedImage_3.png

Best regards,

Vincent.

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jeremyzhou
NXP Employee
NXP Employee

Hi Vincent,

Thanks for your reply.
I'm a bit confused with the second picture, is it a zoomed view of the rising edge as the Fig1 point out?

pastedImage_1.png

Fig 1

Have a great day.

TIC

 

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vincent_rocu
Contributor I

Hello Jeremy,

You correctly understood, the second picture is a zoom view of the area of the first picture where you placed your arrow.

Best regards,

Vincent.

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jeremyzhou
NXP Employee
NXP Employee

Hi Vincent,

Thanks for your clarification.
I also use the oscilloscope to present the SPI transmit process, I find the rising time of the SPI pins is about the several ns.

WeChat Image_20191108191817.jpg
Note that: My board is MIMXRT1060-EVK, and the demo code is evkmimxrt1060_lpspi_lpspi_interrupt_b2b_master which is from the SDK library.

Have a great day.

TIC

 

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vincent_rocu
Contributor I

Hello Jeremy,

Thanks for your test.

On my side, my failled test (under IAR IDE) are the following demo code :

- first test project :

"SDK_2.6.2_EVK-MIMXRT1060\boards\evkmimxrt1060\cmsis_driver_examples\lpspi\int_b2b_transfer"

=> "RC filtered" behaviour of the SPI pin on the arduino header.

- Second test project :

"SDK_2.6.2_EVK-MIMXRT1060\boards\evkmimxrt1060\driver_examples\lpspi\interrupt_b2b"

=> Same "RC filtered" behaviour of the SPI pin on the arduino header.

Can you confirm which SDK you are using? Are you on the revision 2.6.2, or on an older SDK?

Best regards,

Vincent.

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jeremyzhou
NXP Employee
NXP Employee

Hi Vincent,

Thanks for your reply.
I use two MIMXRT1060 boards for testing, one acts the master role, another is the slave, and the boards are set as below.
==============
Weld 0Ω resistor to R278,R279,R280,R281.

SPI one board:
Transfer data from one board instance to another board's instance.
SPI0 pins are connected with SPI0 pins of another board
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
INSTANCE0(SPI0)     CONNECTS TO         INSTANCE0(SPI0)
Pin Name   Board Location     Pin Name  Board Location
SOUT        J24 pin 4           SIN       J24 pin 5
SIN         J24 pin 5           SOUT      J24 pin 4
SCK         J24 pin 6           SCK       J24 pin 6
PCS0        J24 pin 3           PCS0      J24 pin 3
GND         J24 pin 7           GND       J24 pin 7
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Note: int_b2b_transfer demos is from the SDK_2.6.2_EVK-MIMXRT1060.

Have a great day.

TIC

 

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vincent_rocu
Contributor I

Hello Jeremy,

After check, it seems that there was some high value resistors where in the box where I took the 0Ohm straps.

It's all ok now with only 0 Ohm resistors.

Sorry for the mistake, and many thanks for your time!

Vincent.

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jeremyzhou
NXP Employee
NXP Employee

Hi Vincent,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
The default value of SW_PAD_CTL register is 0x10B0, definitely, writing the 0x10b0 won't change the value of SW_PAD_CTL register.
So please use the IOMUXC_SetPinConfig() function to set the value of the SW_PAD_CTL register appropriately.

TIC

 

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