i have been implementing the EMV Spec (SmartCard applications). for a while now with other boards and came across the iMXRT1050 whose power attracted my attention. I immediately bought one and try to port my application to it.
My first challenge is that of creating a phase locked clk signal of about 4MHz. I have imported the Pwm example and adapted the frequence to run with 4MHz, but the signal does not look stable.
I measured it with Saleae Logic analyzer. If you scroll to the right, you would realize, some how the duty cycle seems to have changed.
This is how i changed the main code to look like. I just put out the initialization and start function of the pwm
and also left the duty cycle at 100, because the it is set to 50, when the duty cycle is greater than 99.
This method of generating external clk signal does not fit well. My question is, is there another way of achieving this with this processor?
Hi Derick Beng Yuh,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) This method of generating external CLK signal does not fit well. My question is, is there another way of achieving this with this processor?
-- I'd like to suggest you can try to output the clock source via the CCM_CLKO1 and CCM_CLKO2 instead of utilizing the timer module to generate the PWM if you're unsatisfied with the method.