Has anybody used Macronix MX Flash with iMXRT?

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Has anybody used Macronix MX Flash with iMXRT?

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chriscowdery
Contributor V

Hi,

 We are attemping to use a Macronix MX25L3233F QSPI Flash.

As far as we can tell, it's a drop in replacement for the IS25LP part that the Eval Kit uses, (albeit a different size).

Yet we cannot get it to work reliably.

We are using the Serial Bootloader from the command line, and it's the BLHOST part that fails.

We have investigated activity on the QSPI bus, and it seems that the WRITE is timing out.

Has anybody else tried these parts?

Thanks,

Chris.

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jeremyzhou
NXP Employee
NXP Employee

Thanks for your reply.
1) What does "Quad Mode Entry Setting" to "1 - Set bit 6 in Status Register 1" do?
-- Setting the Quad Enable (QE) bit in the Status Register of the MX25L3233F for support Quad mode.
2) Can you confirm that it writes COMMAND 0x01 to the Flash, setting Bit 6?
-- Yes, and you can learn more information about the Write Status Register (WRSR) sequence (Command 01h) by refer to the MX25L3233F's datasheet.

Have a great day,
TIC

 

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jeremyzhou
NXP Employee
NXP Employee

Hi Chris Cowdery,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
Before answering your question, I'd like to get more information about it.
Whether you can tell me which error message jumps out in the Blhost.
And introduce the other testings you did, as it can help me to figure it out.

Have a great day,
TIC

 

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chriscowdery
Contributor V

Hi Jeremy,

 The error we received was "Data phase write aborted by status 0x2712 kStatus_AbortDataPhase"

We have done more testing, and discovered that we can get a successful Programming by modifing the .bd file "Quad Mode Entry Setting" to "1 - Set bit 6 in Status Register 1"

Once we have programmed a Flash with this set, it can then be programmed with / without this bit set.

We do not know what this 1 - Set bit 6 in Status Register 1" does.

Please can you explain the function of "Set bit 6 in Status Register 1" so we can understand what happens.

Many thanks,


Chris.

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jeremyzhou
NXP Employee
NXP Employee

Hi Chris Cowdery,

Thanks for your reply.
To implement XIP boot with Dual output mode (like Figure 1), it's necessary to set QE bit in the status register to enable the Quad mode.

pastedImage_1.png
BTW: Different QSPI NOR Flash vendors may have different QE bit locations.

Have a great day,
TIC

 

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chriscowdery
Contributor V

Hi Jeremy,

 I am not sure that explains what we see.

We must program the flash with "Quad Mode Entry Setting" to "1 - Set bit 6 in Status Register 1" for the first time only.

Then, we can download .sb files without "Quad Mode Entry Setting" to "1 - Set bit 6 in Status Register 1"

Therefore something inside the Flash must be configured.

We do not have to do with with ISSI flash (MIMXRT1021 EVK), so this setting must change something specific to the Macronix Flash.

We need to know what this "Quad Mode Entry Setting" to "1 - Set bit 6 in Status Register 1" actually does, which register, what effect?

Thanks,

Chris.

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jeremyzhou
NXP Employee
NXP Employee

Hi Chris Cowdery,

Thanks for your reply.
Please refer to the MX25L3233F's datasheet if you want to learn the information about the QE bit and the command to set it.

Have a great day,
TIC

 

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chriscowdery
Contributor V

Hi Jeremy,

 What I need to know is:

What does "Quad Mode Entry Setting" to "1 - Set bit 6 in Status Register 1" do?

Can you confirm that it writes COMMAND 0x01 to the Flash, setting Bit 6?

Thanks,

Chris.

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1,064 Views
jeremyzhou
NXP Employee
NXP Employee

Thanks for your reply.
1) What does "Quad Mode Entry Setting" to "1 - Set bit 6 in Status Register 1" do?
-- Setting the Quad Enable (QE) bit in the Status Register of the MX25L3233F for support Quad mode.
2) Can you confirm that it writes COMMAND 0x01 to the Flash, setting Bit 6?
-- Yes, and you can learn more information about the Write Status Register (WRSR) sequence (Command 01h) by refer to the MX25L3233F's datasheet.

Have a great day,
TIC

 

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chriscowdery
Contributor V

Thankyou Jeremy.

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