FlexSPI read by AHB RX buff on the MIMXRT1050-EVK

[jimmychiang]

Dear Sir.

    Good day!

    I am using the FlexSPI interface to read Flash on MIMXRT1050-EVK.

    But "Software triggered Flash read/write access by IP Bus", that have read latency.

    However, I have read Chapter 30 of the "i.MX RT1050 Processor Reference Manual".

    That have described  "Memory mapped read/write access by AHB Bus". (AHB RX Buffer implemented to reduce read latency.)

    However, I can't understand the description of the "i.MX RT1050 Processor Reference Manual", and there is no such example in the standard SDK.

    So can I download the relevant sample code in NXP web-site ? 

    Or is there a more detailed description of the AHB RX Buffer document?

Thanks!

[art]

This "Memory mapped read/write access by AHB Bus" means that the address space of an external SPI Flash device is directly mapped to the internal AHB bus address space (refer to the Table 2-1 "System memory map" of the i.MX RT1050 Reference Manual document, check the address range of 0x6000_0000 to 0x7F7F_FFFF) so as any master (e.g. CPU core) access to this address range on the AHB bus initiates the access to the corresponding address range of an external SPI Flash device. Of course, the FlexSPI module should be configured appropriately before doing that.

Have a great day,
Artur

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[tkkeiko]

Hello,

I am also a bit confused about this issue.

Can anyone help me?