FlexIO used to compose a parallel data port

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FlexIO used to compose a parallel data port

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giladk
Contributor I
Hi, I'm investigating the possibility to configure a FlexIO block to act as a, kind-of, multi port SPI with 8 data (MOSI) ports and single clock for all data lines, no MISO port(s) and no chip-select ports. I'm trying to do something similar to a parallel port (LPT) which was used in the past to connect a printer to a computer. Final port should work at 25Mhz which means transmitting a total of 25MBytes or 200Mbits per second from memory divided to 8 data ports. Is this possible to do with the FlexIO block? If so, is there any reference design? Tnx Gilad.
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Alexis_A
NXP TechSupport
NXP TechSupport

Hello @giladk,

I think the FlexIO could emulate 8 SPI MOSI with only a single clock and the maximum baud rate achievable by the protocol using as Master is 30Mbps in theory this could be done. But unfortunately, there isn't any reference design/example that shows this functionality. Also, due to the big data handling, this could be tricky to configure and maybe should require implementing other modules as DMA to not saturate MCU.

Sorry for the inconveniences this may cause you.

Best Regards,

Alexis Andalon

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