Error in debug ini file for SDRAM for Keil in SDK for RT117x

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Error in debug ini file for SDRAM for Keil in SDK for RT117x

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carstengroen
Senior Contributor II

I'm using SDK 2.9.2 for RT117x. I have done my own boards with 16 bit SDRAM (single MT48LC16M16 device). CPU is RT1171 at the moment (due to shortage of 1176). Now, in the process of bringing this board up and checking SDRAM in the debugger in Keil, I have stumbled upon an error (I think...)

In the file, evkmimxrt1170_sdram_init.ini the various registers are programmed so the debugger has access to the SDRAM etc. In the function _sdr_init() the IOMUX, PAD control is set

The IOMUX is set correctly for the EMC pins, including EMC_B2_17, EMC_B2_18, EMC_B2_19 and EMC_B2_20. But later in the function where the PAD drive is set, these pins are not set, however EMC_SD_B2_02, EMC_SD_B2_03, EMC_SD_B2_04 and EMC_SD_B2_05 is. I think this is an error (as these signals are used for FlexSPI B and A, and as such has nothing to do with the SDRAM) ?

I have included the (with my comments) the code for the function. 

I think the 4 lines for the PAD control should read:

_WDWORD(0x400E8340, 0x00000008); // EMC_B2_17
_WDWORD(0x400E8344, 0x00000008); // EMC_B2_18
_WDWORD(0x400E8348, 0x00000008); // EMC_B2_19
_WDWORD(0x400E834C, 0x00000008); // EMC_B2_20

 

FUNC void _sdr_Init(void)
{
  // Config IOMUX
  _WDWORD(0x400E8010, 0x00000000); // EMC_B1_00
  _WDWORD(0x400E8014, 0x00000000); // EMC_B1_01
  _WDWORD(0x400E8018, 0x00000000); // EMC_B1_02
  _WDWORD(0x400E801C, 0x00000000); // EMC_B1_03
  _WDWORD(0x400E8020, 0x00000000); // EMC_B1_04
  _WDWORD(0x400E8024, 0x00000000); // EMC_B1_05
  _WDWORD(0x400E8028, 0x00000000); // EMC_B1_06
  _WDWORD(0x400E802C, 0x00000000); // EMC_B1_07
  _WDWORD(0x400E8030, 0x00000000); // EMC_B1_08
  _WDWORD(0x400E8034, 0x00000000); // EMC_B1_09
  _WDWORD(0x400E8038, 0x00000000); // EMC_B1_10
  _WDWORD(0x400E803C, 0x00000000); // EMC_B1_11
  _WDWORD(0x400E8040, 0x00000000); // EMC_B1_12
  _WDWORD(0x400E8044, 0x00000000); // EMC_B1_13
  _WDWORD(0x400E8048, 0x00000000); // EMC_B1_14
  _WDWORD(0x400E804C, 0x00000000); // EMC_B1_15
  _WDWORD(0x400E8050, 0x00000000); // EMC_B1_16
  _WDWORD(0x400E8054, 0x00000000); // EMC_B1_17
  _WDWORD(0x400E8058, 0x00000000); // EMC_B1_18
  _WDWORD(0x400E805C, 0x00000000); // EMC_B1_19
  _WDWORD(0x400E8060, 0x00000000); // EMC_B1_20
  _WDWORD(0x400E8064, 0x00000000); // EMC_B1_21
  _WDWORD(0x400E8068, 0x00000000); // EMC_B1_22
  _WDWORD(0x400E806C, 0x00000000); // EMC_B1_23
  _WDWORD(0x400E8070, 0x00000000); // EMC_B1_24
  _WDWORD(0x400E8074, 0x00000000); // EMC_B1_25
  _WDWORD(0x400E8078, 0x00000000); // EMC_B1_26
  _WDWORD(0x400E807C, 0x00000000); // EMC_B1_27
  _WDWORD(0x400E8080, 0x00000000); // EMC_B1_28
  _WDWORD(0x400E8084, 0x00000000); // EMC_B1_29
  _WDWORD(0x400E8088, 0x00000000); // EMC_B1_30
  _WDWORD(0x400E808C, 0x00000000); // EMC_B1_31
  _WDWORD(0x400E8090, 0x00000000); // EMC_B1_32
  _WDWORD(0x400E8094, 0x00000000); // EMC_B1_33
  _WDWORD(0x400E8098, 0x00000000); // EMC_B1_34
  _WDWORD(0x400E809C, 0x00000000); // EMC_B1_35
  _WDWORD(0x400E80A0, 0x00000000); // EMC_B1_36
  _WDWORD(0x400E80A4, 0x00000000); // EMC_B1_37
  _WDWORD(0x400E80A8, 0x00000000); // EMC_B1_38
  _WDWORD(0x400E80AC, 0x00000010); // EMC_39, DQS PIN, enable SION
  _WDWORD(0x400E80B0, 0x00000000); // EMC_B1_40
  _WDWORD(0x400E80B4, 0x00000000); // EMC_B1_41
  _WDWORD(0x400E80B8, 0x00000000); // EMC_B2_00
  _WDWORD(0x400E80BC, 0x00000000); // EMC_B2_01
  _WDWORD(0x400E80C0, 0x00000000); // EMC_B2_02
  _WDWORD(0x400E80C4, 0x00000000); // EMC_B2_03
  _WDWORD(0x400E80C8, 0x00000000); // EMC_B2_04
  _WDWORD(0x400E80CC, 0x00000000); // EMC_B2_05
  _WDWORD(0x400E80D0, 0x00000000); // EMC_B2_06
  _WDWORD(0x400E80D4, 0x00000000); // EMC_B2_07
  _WDWORD(0x400E80D8, 0x00000000); // EMC_B2_08
  _WDWORD(0x400E80DC, 0x00000000); // EMC_B2_09
  _WDWORD(0x400E80E0, 0x00000000); // EMC_B2_10
  _WDWORD(0x400E80E4, 0x00000000); // EMC_B2_11
  _WDWORD(0x400E80E8, 0x00000000); // EMC_B2_12
  _WDWORD(0x400E80EC, 0x00000000); // EMC_B2_13
  _WDWORD(0x400E80F0, 0x00000000); // EMC_B2_14
  _WDWORD(0x400E80F4, 0x00000000); // EMC_B2_15
  _WDWORD(0x400E80F8, 0x00000000); // EMC_B2_16
  
  _WDWORD(0x400E80FC, 0x00000000); // EMC_B2_17
  _WDWORD(0x400E8100, 0x00000000); // EMC_B2_18
  _WDWORD(0x400E8104, 0x00000000); // EMC_B2_19
  _WDWORD(0x400E8108, 0x00000000); // EMC_B2_20
  
  // PAD ctrl
  // PDRV = 1b (normal); PULL = 10b (PD)
  _WDWORD(0x400E8254, 0x00000008); // EMC_B1_00 
  _WDWORD(0x400E8258, 0x00000008); // EMC_B1_01
  _WDWORD(0x400E825C, 0x00000008); // EMC_B1_02
  _WDWORD(0x400E8260, 0x00000008); // EMC_B1_03
  _WDWORD(0x400E8264, 0x00000008); // EMC_B1_04
  _WDWORD(0x400E8268, 0x00000008); // EMC_B1_05
  _WDWORD(0x400E826C, 0x00000008); // EMC_B1_06
  _WDWORD(0x400E8270, 0x00000008); // EMC_B1_07
  _WDWORD(0x400E8274, 0x00000008); // EMC_B1_08
  _WDWORD(0x400E8278, 0x00000008); // EMC_B1_09
  _WDWORD(0x400E827C, 0x00000008); // EMC_B1_10
  _WDWORD(0x400E8280, 0x00000008); // EMC_B1_11
  _WDWORD(0x400E8284, 0x00000008); // EMC_B1_12
  _WDWORD(0x400E8288, 0x00000008); // EMC_B1_13
  _WDWORD(0x400E828C, 0x00000008); // EMC_B1_14
  _WDWORD(0x400E8290, 0x00000008); // EMC_B1_15
  _WDWORD(0x400E8294, 0x00000008); // EMC_B1_16
  _WDWORD(0x400E8298, 0x00000008); // EMC_B1_17
  _WDWORD(0x400E829C, 0x00000008); // EMC_B1_18
  _WDWORD(0x400E82A0, 0x00000008); // EMC_B1_19
  _WDWORD(0x400E82A4, 0x00000008); // EMC_B1_20
  _WDWORD(0x400E82A8, 0x00000008); // EMC_B1_21
  _WDWORD(0x400E82AC, 0x00000008); // EMC_B1_22
  _WDWORD(0x400E82B0, 0x00000008); // EMC_B1_23
  _WDWORD(0x400E82B4, 0x00000008); // EMC_B1_24
  _WDWORD(0x400E82B8, 0x00000008); // EMC_B1_25
  _WDWORD(0x400E82BC, 0x00000008); // EMC_B1_26
  _WDWORD(0x400E82C0, 0x00000008); // EMC_B1_27
  _WDWORD(0x400E82C4, 0x00000008); // EMC_B1_28
  _WDWORD(0x400E82C8, 0x00000008); // EMC_B1_29
  _WDWORD(0x400E82CC, 0x00000008); // EMC_B1_30
  _WDWORD(0x400E82D0, 0x00000008); // EMC_B1_31
  _WDWORD(0x400E82D4, 0x00000008); // EMC_B1_32
  _WDWORD(0x400E82D8, 0x00000008); // EMC_B1_33
  _WDWORD(0x400E82DC, 0x00000008); // EMC_B1_34
  _WDWORD(0x400E82E0, 0x00000008); // EMC_B1_35
  _WDWORD(0x400E82E4, 0x00000008); // EMC_B1_36
  _WDWORD(0x400E82E8, 0x00000008); // EMC_B1_37
  _WDWORD(0x400E82EC, 0x00000008); // EMC_B1_38
  _WDWORD(0x400E82F0, 0x00000008); // EMC_39, DQS PIN, enable SION
  _WDWORD(0x400E82F4, 0x00000008); // EMC_B1_40
  _WDWORD(0x400E82F8, 0x00000008); // EMC_B1_41
  _WDWORD(0x400E82FC, 0x00000008); // EMC_B2_00
  _WDWORD(0x400E8300, 0x00000008); // EMC_B2_01
  _WDWORD(0x400E8304, 0x00000008); // EMC_B2_02
  _WDWORD(0x400E8308, 0x00000008); // EMC_B2_03
  _WDWORD(0x400E830C, 0x00000008); // EMC_B2_04
  _WDWORD(0x400E8310, 0x00000008); // EMC_B2_05
  _WDWORD(0x400E8314, 0x00000008); // EMC_B2_06
  _WDWORD(0x400E8318, 0x00000008); // EMC_B2_07
  _WDWORD(0x400E831C, 0x00000008); // EMC_B2_08
  _WDWORD(0x400E8320, 0x00000008); // EMC_B2_09
  _WDWORD(0x400E8324, 0x00000008); // EMC_B2_10
  _WDWORD(0x400E8328, 0x00000008); // EMC_B2_11
  _WDWORD(0x400E832C, 0x00000008); // EMC_B2_12
  _WDWORD(0x400E8330, 0x00000008); // EMC_B2_13
  _WDWORD(0x400E8334, 0x00000008); // EMC_B2_14
  _WDWORD(0x400E8338, 0x00000008); // EMC_B2_15
  _WDWORD(0x400E833C, 0x00000008); // EMC_B2_16
  
  _WDWORD(0x400E8400, 0x00000008); // EMC_SD_B2_02  <<---- This is an error ? I think these 4 lines should be for EMC_B2_17..EMC_B2_20 instead
  _WDWORD(0x400E8404, 0x00000008); // EMC_SD_B2_03
  _WDWORD(0x400E8408, 0x00000008); // EMC_SD_B2_04
  _WDWORD(0x400E840C, 0x00000008); // EMC_SD_B2_05

  // Config SDR Controller Registers/
  _WDWORD(0x400d4000,0x10000004); // MCR
  _WDWORD(0x400d4008,0x00000081); // BMCR0
  _WDWORD(0x400d400C,0x00000081); // BMCR1
  //_WDWORD(0x400d4010,0x8000001D); // BR0, 64MB
  _WDWORD(0x400d4010,0x8000001B); // BR0, 32MB
  
  //_WDWORD(0x400d4040,0x00000F32); // SDRAMCR0, 32bit
  _WDWORD(0x400d4040,0x00000F31); // SDRAMCR0, 16bit
  
  _WDWORD(0x400d4044,0x00772A22); // SDRAMCR1
  _WDWORD(0x400d4048,0x00010A0D); // SDRAMCR2
  _WDWORD(0x400d404C,0x21210408); // SDRAMCR3
                        
  _WDWORD(0x400d4090,0x80000000); // IPCR0
  _WDWORD(0x400d4094,0x00000002); // IPCR1
  _WDWORD(0x400d4098,0x00000000); // IPCR2

  
  _WDWORD(0x400d409C,0xA55A000F); // IPCMD, SD_CC_IPREA
  SDRAM_WaitIpCmdDone();
  _WDWORD(0x400d409C,0xA55A000C); // SD_CC_IAF
  SDRAM_WaitIpCmdDone();
  _WDWORD(0x400d409C,0xA55A000C); // SD_CC_IAF
  SDRAM_WaitIpCmdDone();
  _WDWORD(0x400d40A0,0x00000033); // IPTXDAT
  _WDWORD(0x400d409C,0xA55A000A); // SD_CC_IMS
  SDRAM_WaitIpCmdDone();
  _WDWORD(0x400d4150,0x00000017); // DCCR
  _WDWORD(0x400d404C,0x21210409 ); // enable sdram self refresh again after initialization done.
}

 

 

 

 

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carstengroen
Senior Contributor II

.

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jingpan
NXP TechSupport
NXP TechSupport

Hi @carstengroen ,

yes, this .ini code is a bit confusing. The EVK board use QSPI as default NVM memory. It needn't initialize Hypherflash pins. EMC_B2_17 is used as SEMC_DM3, its pad control register should be set. EMC_B2_18 is used as DQS, it is floating. EMC_B2_19 and EMC_B2_20 is now working as ENET pin. They should not be configured here. 

I'll report it to software team.

 

Regards,

Jing

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carstengroen
Senior Contributor II

Hi Jing,

thanks for confirming my suspicion

Regards,

Carsten

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