I was taking a look at the evkmimxrt1020_enet_txrx_transfer reference to check out the clocking configuration and noticed that it doesn't generate the 2.5MHz MDC clock speed that is stated in the code:
/* Set SMI to get PHY link status. */ sysClock = CORE_CLK_FREQ; status = PHY_Init(EXAMPLE_ENET, EXAMPLE_PHY, sysClock);
The error is at the line above in red. The core clock is not the correct clock. It should be IPG clock instead.
The reference works by chance because the value calculated overflows from the calculated 100 (which is not possible) to 72. IPG is core/4 in the reference (150MHz) and so the 1.7MHz MDC happens to be generated.
That is, it physically works but uses incorrect clock assignment.