ENET RMII Connections

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ENET RMII Connections

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jautry
Contributor IV

I am confused about the REF_CLK inputs on the MIMXRT1062.  The reference manual has them as inputs but in the eval kits they appear to be used as outputs.  I am running in RMII mode, do these pins also provide 50mhz outputs??

Also, if configured as REF_CLK input in RMII mode.  I assume these inputs are required to be 50mhz clocks.  I was providing the txclock from the phy which used a fixed 50mhz oscillator but divided down the txclock to 25mhz which I am assuming will not be correct, and that I need to tie them directly to the 50mhz.  Is this correct?

 

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Jautry,

The REF_CLK signal can be used as input or output when in RMII mode. I think there were some changed made to the Reference Manual on the last revision as it wasn’t very clear.

When REF_CLK pin is used as an input you would use:

bit ENET1_TX_CLK_DIR = 0 in IOMUX_GPR_GPR1 register

bit ENET1_CLK_SEL = 1 in IOMUX_GPR_GPR1 register

 

If you would use it as output to feed the PHY  then REF_CLK pin would be an output and you would use:

bit ENET1_TX_CLK_DIR = 1 in IOMUX_GPR_GPR1 register

bit ENET1_CLK_SEL = 0 in IOMUX_GPR_GPR1 register

You would also need to configure the refenet_pll clock to 50MHz.

DIV_SELECT = 1 in CCM_ANALOG_PLL_ENET register

ENABLE = 1 in CCM_ANALOG_PLL_ENET register

I hope that this information helps!

Regards,
Gustavo

 

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Jautry,

The REF_CLK signal can be used as input or output when in RMII mode. I think there were some changed made to the Reference Manual on the last revision as it wasn’t very clear.

When REF_CLK pin is used as an input you would use:

bit ENET1_TX_CLK_DIR = 0 in IOMUX_GPR_GPR1 register

bit ENET1_CLK_SEL = 1 in IOMUX_GPR_GPR1 register

 

If you would use it as output to feed the PHY  then REF_CLK pin would be an output and you would use:

bit ENET1_TX_CLK_DIR = 1 in IOMUX_GPR_GPR1 register

bit ENET1_CLK_SEL = 0 in IOMUX_GPR_GPR1 register

You would also need to configure the refenet_pll clock to 50MHz.

DIV_SELECT = 1 in CCM_ANALOG_PLL_ENET register

ENABLE = 1 in CCM_ANALOG_PLL_ENET register

I hope that this information helps!

Regards,
Gustavo

 

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