Debug issues with custom RT1062 HW, MCUXpresso 10.3.1

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Debug issues with custom RT1062 HW, MCUXpresso 10.3.1

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gpontis
Contributor IV

My custom hardware built around a RT1062 doesn't have HyperFlash, so development is currently limited to running from RAM. The board also does not have an USB debug adapter, only a 20 pin Cortex debug+trace connection. I have had various different issues with connecting debug probes.

A Segger JLink Ultra+ seems to work in most cases, but does not connect in JTAG mode, only SWD. It starts up quickly and feels very responsive. I previously reported that I had trouble running the demo apps when linked to RAM. Victor reported that in his experience it was related to the JLink, as the was no problem when using on the board debug circuits of the demo board, or other probes including the LPC-Link2.

I purchased a LPC-Link2 to try. It will not connect if BOOT_MODE[1] is pulled up at startup. This is my default configuration since the board's flash is on LPSPI3. I am attaching an screen shot showing the error message. If possible, the startup scripts should handle either situation and ensure that the debug environment is consistent.

The LPC-Link2 does connect if BOOT_MODE[1:0] are left to default or grounded, but does not operate reliably with my hardware. For example, I load an app and it runs to a breakpoint. It fails if I try to step with "16: Target error message from status-poll". I would like to try it with a demo board but only have the 1050 EVKB, which does not have a Cortex debug connector for the 1050.

Going back to the JLink, I noticed that the installation of MCUXpress 10.3.1 seems to have silently installed a newer version of the JLink software package, 6.42b. Is there any documentation on the reason for this ?

What are you others doing for debug probes on custom hardware ?

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi George Points,

   When you use the LPC-LINK2 JLINK to connect your RT1062, please use the JLINK command check whether you can find the Cortex M7 core or not?

pastedImage_1.png

Please check this point at first.

Just check whether your hardware have problems or not.

BTW, what the firmware in your LPC-LINK2 now? CMSIS DAP?

The LPC-LINK2 can use CMSIS DAP or JLINK firmware, it use this software to change the debugger firmware:

www.nxp.com/lpcscrypt

After you check the core connection, please let me know the new test result.

Kerry

 

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gpontis
Contributor IV

Hi Kerry,

Connection with a Segger JLink seems to work properly in SWD mode. I will append a screen dump. The LPC Link2 has CMSIS DAP V5.182 software installed but I let it load using DFU from MCUXpresso. It reports "CMSIS DAP V5.224". I connect the LPC Link2 to J8 since my target has the 20 pin Cortex debug connector with trace. Is it your recommendation to reflash the Link2 with JLink software and try that instead?

George

Connection with Segger JLink Ultra+

J-Link>connect
Please specify device / core. <Default>: MIMXRT1062DVL6A
Type '?' for selection dialog
Device>
Please specify target interface:
J) JTAG (Default)
S) SWD
T) cJTAG
TIF>s
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "MIMXRT1062DVL6A" selected.


Connecting to target via SWD
InitTarget() start
InitTarget()
_TargetHalt: CPU halted
InitTarget() end
Found SW-DP with ID 0x0BD11477
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770041)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FD000
CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
Found Cortex-M7 r1p1, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FD000
ROMTbl[0][0]: E00FE000, CID: B105100D, PID: 000BB4C8 ROM Table
ROMTbl[1] @ E00FE000
ROMTbl[1][0]: E00FF000, CID: B105100D, PID: 000BB4C7 ROM Table
ROMTbl[2] @ E00FF000
ROMTbl[2][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[2][1]: E0001000, CID: B105E00D, PID: 000BB002 DWT
ROMTbl[2][2]: E0002000, CID: B105E00D, PID: 000BB00E FPB-M7
ROMTbl[2][3]: E0000000, CID: B105E00D, PID: 000BB001 ITM
ROMTbl[1][1]: E0041000, CID: B105900D, PID: 001BB975 ETM-M7
ROMTbl[1][2]: E0042000, CID: B105900D, PID: 004BB906 CTI
ROMTbl[0][1]: E0040000, CID: B105900D, PID: 000BB9A9 TPIU-M7
ROMTbl[0][2]: E0043000, CID: B105F00D, PID: 001BB101 TSG
Cache: Separate I- and D-cache.
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
Cortex-M7 identified.
J-Link>

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi George Points,

    Yes, I recommend you to use the JLINK firmware in th LPC-LINK2.

    From your log, your ARM Cortex M7 core can be found with the JLINK.

   Now, do you debug your chip with the RAM directly, it should work OK.

  You can try to debug the code in the RAM, not in the external flash at first.

   Because the external flash debug also related to the flash configuration, it is related to your external flash chip.

  Please try the RAM debug at first, can you make it work?

 Any updated information, please kindly let me know.

Have a great day,
Kerry

 

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gpontis
Contributor IV

Hi Kerry,

I downloaded and flashed the LPC-Link2 with JLink software, and ran JLink COmmander to try to connect to my target. In JTAG mode it does not connect and gives similar messages  to the Segger JLink. It does connect and recognize the core in SWD mode, just like the Segger JLink, but then puts forth an error message about the firmware not being suitable for this Cortex-M7. I am attaching a screen shot. I have ordered a 1064 eval board so I can try the LPC-Link2 and see how it may be different from my target hardware.

 

My board does not have any flash except an SPI memory on LPSPI3, and I have not tackled that problem of booting from it yet. So the _only_ debugging that I have done has been when running from RAM. I can run quite a bit of code like this but no ethernet and no USB. In a different thread I reported that when using a JLink, even the demo USB or ethernet apps would not run on an eval board if linked to run from RAM. Victor tried it and found the same thing. I would have to believe that it is some kind of a setup or config issue but am hoping some higher powers will intercede with a solution before I have to try tracking it down.

George 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Geoge,

    No, RT1064 board have the internal flash, you need to use MIMXRT1060-EVB board.

   I can't find our screen shot, please attached it again.

   What's the external flash you are using in your own board now?

  About the code, you can use the SDK code directly.

Welcome | MCUXpresso SDK Builder 

  Then delete the flash, and test it in your board.

  Any question, please give me the screen shot.

   


Have a great day,
Kerry

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gpontis
Contributor IV

I am using a 64Mb SPI flash, SST26VF064BT. Schematic attached. The connection is working OK at run time but I have yet to build the image that is required to boot from it. Also I will need to figure out how to "blow" one of the fuses due to my choice of chip select. I do have MCUXpresso 10.3.1 and SDK 2.5.0. Am I understanding from your post that it can build the SPI flash image that I need to write to this flash ? That would be helpful. With regard to the LPC-Link2, what adapter do you use to connect to the old style ARM debug connector used on the demo boards ? 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi George Pontis,

    Please refer to these application:

How to Enable Boot from QSPI Flash
How to Enable Debugging for FLEXSPI NOR Flash

It's better to use these flash in the list:

pastedImage_1.png

pastedImage_2.png

These flash according configuration parameter already can be found in the flashloader, but your flash is not in the list.


Have a great day,
Kerry

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