DDR mode for QSPI in IMXRT1021

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

DDR mode for QSPI in IMXRT1021

Jump to solution
3,199 Views
vishaljoshi
Contributor I

We are booting out of QSPI flash fine in SDR mode. I am now trying to boot from QSPI flash with DDR mode so that we can reduce clock speed. I am trying following settings, but no luck. Has anyone used DDR before:

flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClksrc=kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.controllerMiscOption = kFlexSpiMiscOffset_DdrModeEnable,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_50MHz,
.sflashA1Size = 8u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
/*FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),*/
FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_1PAD, 0xED, RADDR_DDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_DDR, FLEXSPI_4PAD, 0x06, READ_DDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 64u * 1024u,
.isUniformBlockSize = false,
};

0 Kudos
1 Solution
3,162 Views
jeremyzhou
NXP Employee
NXP Employee

Hi,
Thanks for your reply.
According to the Fig 1, the DDR mode is only supported with specific QSPI flashs, in another word, the DDR mode isn't able to be configure manually.
Have a great day,
TIC

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

 

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

View solution in original post

0 Kudos
8 Replies
3,078 Views
vishaljoshi
Contributor I

Hi Jeremy,

Our initial analysis is incorrect. DDR Mode works on QSPI Flash IS25LP064A. Please find attached settings. I received these settings from NXP ticket support. I tried these on RT1021 Dev board. Board is booting off QSPI in DDR.

 

Thank you.

Regards,

Vishal

0 Kudos
3,183 Views
vishaljoshi
Contributor I

Hi Jeremy,

I am using IS25LP064A. It supports DTR up to 66MHz. So I have setup clock to 50MHz and instruction changed to 0xED. I have attached snapshot for your reference.

Thank you.

With regards,

  Vishal

0 Kudos
3,179 Views
vishaljoshi
Contributor I

Hi Jeremy,

I have ordered different die to try - IS25LP064D-JBLA3. As per datasheet, this die D supports DTR up to 80MHz. Let me try it on Monday and I will share results. As far as settings go, do you see any additional settings to be changed? Thank you for help.

const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClksrc=kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.controllerMiscOption = kFlexSpiMiscOffset_DdrModeEnable,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_30MHz,
.sflashA1Size = 8u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
/*FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),*/
FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_1PAD, 0xED, RADDR_DDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_DDR, FLEXSPI_4PAD, 0x06, READ_DDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 64u * 1024u,
.isUniformBlockSize = false,
};

With regards,

   Vishal

0 Kudos
3,193 Views
jeremyzhou
NXP Employee
NXP Employee

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
To provide the fastest possible support, I'd highly recommend you to check your flash chip whether can work in DDR mode, meanwhile, it is supported by the i.MX RT1020 too.

jeremyzhou_0-1614914795766.png


Have a great day,
TIC

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

 

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

0 Kudos
3,167 Views
vishaljoshi
Contributor I

Hi Jeremy,

I tried IS25LP064D. This part supports DDR. I have enabled Quad Enable bit. But still I am unable to boot from QSPI in DDR mode. SDR mode is working OK. I can boot in SDR mode from NOR flash.

Do you have any other suggestion?

Thank you.

With regards,

 Vishal

0 Kudos
3,163 Views
jeremyzhou
NXP Employee
NXP Employee

Hi,
Thanks for your reply.
According to the Fig 1, the DDR mode is only supported with specific QSPI flashs, in another word, the DDR mode isn't able to be configure manually.
Have a great day,
TIC

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

 

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

0 Kudos
3,123 Views
vishaljoshi
Contributor I

Hi Jeremy,

So it looks like DDR booting is not supported on QSPI flash. Thank you for helping us to reach conclusion.

With regards,

   Vishal

0 Kudos
3,074 Views
jay_heng
NXP Employee
NXP Employee

DDR mode can be enabled for QSPI in i.MXRT

Your provided FDCB is incorrect, please refer my post

https://www.cnblogs.com/henjay724/p/14682888.html