Controlling HS USB and Ethernet bus arbitration (i.MX RT 1062)

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Controlling HS USB and Ethernet bus arbitration (i.MX RT 1062)

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mjbcswitzerland
Specialist V

Hi All

In an environment with HS USB host and Ethernet on the i.MX RT 1062 we are finding that there are some Ethernet CRC errors being detected and it looks to happen when the HS USB is performing transfers at the same time.

Since the Ethernet reception is controlled by HW (dedicated DMA to RAM) it is expected that the issue is that the HS USB's bus master is not allowing the Ethernet bus master adequate resources for it to ensure that it can save the received data - the result being that Ethernet Rx bytes are lost, resulting in CRC32 errors on the Ethernet bus.

What possibilities does the processor have to control the bus master's priorities or load balancing that may be used to avoid such issues?

Thanks!

Regards

Mark

 

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Seif
NXP Employee
NXP Employee

Hello @mjbcswitzerland,

I think you should consult  Chapter 29: Network Interconnect Bus System
it is a configurable AXI arbiter between several masters and slaves
That will help you increase priority as you need.

Please check following specifically:

Seif_0-1652960346172.png

 

You might also need to increase priority of DMA 

Seif_1-1652960397436.png

 

@mjbcswitzerland you said you opened a support case. Please close this one by marking it helpful/solved.
And we will continue support in the case (as you might reveal more details about your specific architecture)

Thank you in advance,
Best regards
Seif

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4 Replies
403 Views
Seif
NXP Employee
NXP Employee

Hello @mjbcswitzerland,

I think you should consult  Chapter 29: Network Interconnect Bus System
it is a configurable AXI arbiter between several masters and slaves
That will help you increase priority as you need.

Please check following specifically:

Seif_0-1652960346172.png

 

You might also need to increase priority of DMA 

Seif_1-1652960397436.png

 

@mjbcswitzerland you said you opened a support case. Please close this one by marking it helpful/solved.
And we will continue support in the case (as you might reveal more details about your specific architecture)

Thank you in advance,
Best regards
Seif

373 Views
mjbcswitzerland
Specialist V

Hi

Many thanks for pointing out the NIC-301.

I have downloaded the ARM document "CoreLink™ Network Interconnect NIC-301 Revision: r2p3"

Looking at the bus master priorities I see that Ethernet is set up in the device to have a priority of 3 and the HSUSB to have a priority of 2, which I also verified by reading the core's registers, which would suggest that HS USB will not cause the Ethernet receptions to be blocked by its own operation.

I'll do some further testing though and contact you in the support case should the situation not be improved by this work.

Thanks

Regards

Mark

 

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mjbcswitzerland
Specialist V

Hi

Any ideas on this?

Regards

Mark

 

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433 Views
mjbcswitzerland
Specialist V

Hi

Any ideas?

A support case was also opened but the question has also resulted in silence there too.

Thanks

Regards

Mark

 

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