Capacitors request for NVCC_EMCx power source.

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Capacitors request for NVCC_EMCx power source.

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takayuki_ishii
Contributor IV

Hello community,

 

I have a question about supply capacitors request table.

 

In Table 1. Processor supply capacitors when on-chip DCDC regulators are used of document

Hardware Development Guide for the MIMXRT1160/1170 Processor , Rev. 2, 09/2021,

It say that

Power rail0.1 μF0.22 μF1 μF2.2 μF4.7 μF22 μFNotes
NVCC_EMC1_X   11 Place2.2 μF under balls F6, F7
NVCC_EMC2_X   11 Place 2.2 μF under balls H6, J6

 

It is meaning that the three power lines(NVCC_EMC1_1, NVCC_EMC1_2, NVCC_EMC1_3) require one 2.2uF and one 4.7uF, one under the F6 ball and the other under the F7 ball.

Each of the three power lines does not individually require 2.2uF and 4.7uF.

 

Is this understanding is correct?

 

Best regards,

Ishii.

 

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PabloAvalos
NXP TechSupport
NXP TechSupport

Hi @takayuki_ishii 

 

Please accept my apologies for the delay, I was out of the office a couple of days due a personal situation. I highly appreciate your patience.

 

Regarding your question, and after double-checking, the correct one is as you mentioned at the end, as it shown on the diagram, 1 x 2.2uF + 1 x 4.7uF for all those 3 lines (F7/F6/G6).

 

Hope it was helpful, please let me know if you have more questions.

 

Thank you.
Best Regards.
Pablo Avalos.

 

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PabloAvalos
NXP TechSupport
NXP TechSupport

Hi @takayuki_ishii 

 

Thank you so much for using our community. I am here to assist you. I really appreciate your patience.

 

In order to help you with your request, may you clarify to me what do you mean with your question about each of those three power lines does not individually require those capacitors? Because based on the table, it says that each power line needs both capacitors.

 

I will stay tuned to your reply, so please let me know if you have more questions.

 

Best Regards.
Pablo Avalos.

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takayuki_ishii
Contributor IV

Hello @PabloAvalos 

 

Thank you for your reply.

And sorry my wrong question.

 

Power rail0.1uF0.22uF1uF2.2uF4.7uF22uFNotes
NVCC_EMC1_X   11 Place under balls F7, G6

 

mean that

1)

Power rail0.1uF0.22uF1.uF2.2uF4.7uF22uF

Notes

NVCC_EMC1_1

NVCC_EMC1_2

NVCC_EMC1_3

   11 

Place under balls

F7->2.2uF

G6->4.7uF

 

or

2)

Power rail0.1uF0.22uF1uF2.2uF4.7uF22uFNotes
NVCC_EMC1_1   11 

 

NVCC_EMC1_2   11 

 

NVCC_EMC1_3   11 

 

 

Which is correct answer?

From schematic of RT1170-EVK, it seems that 1x 2.2uF and 1x 4.7uF for 3 ball(NVCC_EMC1_1, NVCC_EMC1_2, NVCC_EMC1_3) is correct.

Is it OK?

takayuki_ishii_0-1646091946494.png

 

Best regards,

Ishii.

 

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1,182 Views
PabloAvalos
NXP TechSupport
NXP TechSupport

Hi @takayuki_ishii 

 

Please accept my apologies for the delay, I was out of the office a couple of days due a personal situation. I highly appreciate your patience.

 

Regarding your question, and after double-checking, the correct one is as you mentioned at the end, as it shown on the diagram, 1 x 2.2uF + 1 x 4.7uF for all those 3 lines (F7/F6/G6).

 

Hope it was helpful, please let me know if you have more questions.

 

Thank you.
Best Regards.
Pablo Avalos.

 

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takayuki_ishii
Contributor IV

Hello @PabloAvalos 

 

Thank you for your reply.

Is the same rule applied to these two power lines?

Power rail0.1uF0.22uF1uF2.2uF4.7uF22uFNotes
VDD_SOC_IN_x  2 31Place 0402 under balls H8, J8, J9,J10, K10
NVCC_EMC2_X   11 Place under balls H6, J6

 

Best regards,

Ishii.

 

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