Can we use a XIP flash and a data flash at the same FlexSPI controller?

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Can we use a XIP flash and a data flash at the same FlexSPI controller?

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Senior Contributor I

Hello,

the reference manual of RT1020 shows how to connect flash devices to FlexSPI (RT1020 has only 4 data lines for A and 4 for B not 8 as shown in the picture)

pastedImage_1.png

We want to use XIP on Flash A1 (read only) and Flash B1 as data flash (read and write).

Is it possible to XIP from A1 and write to the second Flash at the same time or will this reduce XIP performance because FlexSPI has to wait for the next XIP read until the write cycle (=erase + write) of Flash B1 is finished?

Does a read of Flash B1 overwrite the prefetch buffer of Flash A1 and therefore reduce XIP performance or does every flash have it's own prefetch buffer?

If we use parallel mode we can use two QSPI at the same time,

pastedImage_2.png

but can we still use A1 for XIP (read only) and B1 for data (read and write)?

Kind regards,

Stefan

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NXP TechSupport
NXP TechSupport

Hi Stefan,

Yes, you can use A1 to XIP while use B1 to save data. XIP use AHB bus. Program use IPS bus.

While you XIP and program at same time, it almost won't reduce performance. Because FlexSPI has buffer.

If you use them in parallel mode, you can't use A1 for XIP and B1 for XIP. Because there data is integrated as one byte. They have same address space.

Regards,

Jing

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Contributor II

Hi Stefan,

I have the same use case as that of yours where I have flash A1 running XIP and flash B1 for data read/write. I'm having issues with configuring my 2nd QSPI flash. It would be great if you can share your flash initialization. The AN12564 has both flashes running XIP and are connected to the same port, as well which is a different situation. 

Thanks,

Thivya

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Senior Contributor I

Hello Thivya Ashok Kumar,

I am sorry but I'm not allowed to share the complete code.

What I'm doing for initialization is the following:

  1. Disable interrupts and AHB prefetch
  2. FLEXSPI_Init
  3. FLEXSPI_SetFlashConfig for all flash devices
  4. FLEXSPI_UpdateLUT
  5. FLEXSPI_SoftwareReset
  6. Enable interrupts (AHB prefetch will be initialized by FLEXSPI_Init)

Be careful with the location of your configuration structures, LUT table and functions. For initialization they have to be located in RAM (don't forget the fsl_flexspi.o and fsl_clock.o module functions).

Kind regards,

Stefan

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Contributor I

Hi Stefan,could you upload your flexspi initial code with photo? I still cannot success to access to flash B1.

Thanks,

Dylan

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Senior Contributor I

Hello Dylan,

sorry, but as I said above - I can't upload my code.

Maybe open a new thread and upload your code. Somebody from NXP will take a look at it.

Kind regards,

Stefan

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Contributor III

Hi Stefan,

I think AN12564 addresses your use case.

Armand

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NXP TechSupport
NXP TechSupport

Hi Stefan,

Yes, you can use A1 to XIP while use B1 to save data. XIP use AHB bus. Program use IPS bus.

While you XIP and program at same time, it almost won't reduce performance. Because FlexSPI has buffer.

If you use them in parallel mode, you can't use A1 for XIP and B1 for XIP. Because there data is integrated as one byte. They have same address space.

Regards,

Jing

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Senior Contributor I

Hi Jing and thank you for your answer!

I have one more question: if we read Data from flash B1 with AHB bus will this overwrite the AHB prefetch buffer for XIP (flash A1)?

Kind regards,

Stefan

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NXP TechSupport
NXP TechSupport

Hi,

Yes, I think so. After all, A and B share same AHB buffer.

Regards,

Jing

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Senior Contributor I

Thank you!

Kind regards,

Stefan

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