CSI Clock

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CSI Clock

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jaredm
Contributor III

We are developing hardware using the RT1052 and a 12-bit parallel CMOS sensor. We intended to clock the CSI peripheral at 72 MHz (80 MHz Max - 10% margin) and configure the CSI_MCLK as 12 MHz or 8 MHz. The CSI_MCLK would then be multiplied in the CMOS sensor to produce a CSI_PIXCLK of 24 MHz.

Unfortunately I don't think this is possible. The Reference Manual states "MCLK is provided by the CCM module directly, not from the CSI module itself." It appears that the same clock used for the CSI peripheral is used for CSI_MCLK - and that CSI_MCLK does not have it's own divider in the CCM module or otherwise. Can someone confirm if this is indeed true?

If it is true, the CSI peripheral clock and CSI_MCLK will be configured as 12 MHz, and CSI_PIXCLK will be 24 MHz. Are there any issues when the CSI peripheral clock < CSI_PIXCLK? I don't think there will be, because it appears that the RxFIFO is clocked independently of the CSI peripheral. But, I wanted to double check.

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jaredm
Contributor III

Hi Gustavo,

Since it is unclear whether I can have MCLK = 12MHz and PIXCLK = 24-36 MHz, it might be easier to generate MCLK using a different peripheral. On RT1052, GPIO_B1_15 is shared with CSI_MCLK and FLEXIO2_D31, so I have the option of using either CSI or FlexIO to generate the clock. Using FlexIO, I implemented a 12 MHz PWM wave with 50% duty cycle. If further clarification is provided regarding CSI clocking, I can revisit using the CSI peripheral to generate the clock.

Regards,

jaredm

 

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jaredm
Contributor III

The attached image is from the i.MX RT 1050 reference manual. The CSI peripheral uses several different clocks, all gated by CCGR2[CG1]. Is CSI_HCLK only used by CSI_MCLK, which is then fed to the respective IOMUXC'es? Or is CSI_HCLK also used by other logic in the CSI peripheral?

 

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Jaredm,

The CSI_MCLK is generated by the CCM, as shown in figure 14-2 of the i.MXRT1050 Reference Manual

There is a post divider for this clock, as part of the CCM. It can be configured by the CSCDR3[CSI_PODF] bits.

As for the CSI pixel clock it can be asynchronous to the module clock. I’m not sure I have seen implementations where is higher than the module clock, but the critical relationship is that HCLK needs to be at least ten percent faster than the pixel clock.

Regarding the relationship between CSI_HCLK and CSI_MCLK, these are generated independently as you may find in the CCM tree, and both are used by the CSI module but there is not much documentation on the inner workings of this module, other than what’s included in the Datasheet and Reference Manual.

I can investigate if there is more details available but would you please elaborate a bit more on your desired application and all the information that you need regarding the relationship of the CSI clocks.

Regards,
Gustavo

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jaredm
Contributor III

Hi Gustavo,

Since it is unclear whether I can have MCLK = 12MHz and PIXCLK = 24-36 MHz, it might be easier to generate MCLK using a different peripheral. On RT1052, GPIO_B1_15 is shared with CSI_MCLK and FLEXIO2_D31, so I have the option of using either CSI or FlexIO to generate the clock. Using FlexIO, I implemented a 12 MHz PWM wave with 50% duty cycle. If further clarification is provided regarding CSI clocking, I can revisit using the CSI peripheral to generate the clock.

Regards,

jaredm

 

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