Access to flexspi registers takes 60 ns per instruction

[nyontchev]

We are using flexspi bus to read data from FPGA. with iMX RT 600 MHz processor. We have found out the access to the plexspi control registers is very slow. We have measured 60 nano seconds for reads and the same for writing. For example

base->ISR = mask;

takes 60 ns and we would like to know if this is what it takes to communicate from 600 MHz bus to the much slower 150 MHz bus or may be we haven't configured correctly our device?

Thank you,

Nik

[kerryzhou]

Hi Nikolay Iontchev,

   Please check your assembly code about :

base->ISR = mask;

  in your project.

  Then the core clock is 600 MHz, you can check each asm ARM instruction time, you also can calculate that code time.

  BTW, I think you also can try to add some code optimization level in your project, it may shorten the code execution time.

Wish it helps you!

If you still have questions about it, please kindly let me know.

Have a great day,
Kerry

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[nyontchev]

Hi Kerry,

We have examined the assembly code and it is correct and optimized. The problem is that a single write or read to the register takes approx. 40 processor cycles on a 600 MHz processor (60 nanoseconds). I would like to know from somebody who has experience with the SPI and SPI configuration if this is expected access time.

Nik

[kerryzhou]

Hi Nikolay Iontchev,

   What's the IDE you are using? Please debug your code, then check your C code

base->ISR = mask;

related assembly code , then you can use the ARM instruction to calculate the detail processor cycles about this single C code.

Have a great day,
Kerry

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