About the RT600 clock

[keita_yamasaki]

Customers are currently developing radios using the RT600.
I am sorry that the following phenomenon is occurring, but I would appreciate it if you could give me some advice.

Input the 18MHz Clock to P2_15 of MIMXRT685-EVK from the outside and use it as CLKIN.
And when AUDIO-PLL is bypassed, the phenomenon that AUDIOPLLCLKDIV and CLKOUTDIV in the latter stage do not become stable occurs.

By the way, it works when the input is set to "external XTAL 24MHz" or "built-in 48MHz".
Therefore, I think there is a problem with the external clock input, but what is the possible cause?

Remarks
I'm using the SDK.
"PLL register information" is set in the Config Tool. I will attach a capture of the setting screen of Config Tool.

CLKIN is selected in SYSOS CBYPASS at the upper left.
Clk_in is selected in AUDIOPLLOCLKSEL at the bottom left.
On the right side, BYPASS is selected in AUDIOPLL0_PFD0_BYPASS.
At this time, the part of AUDIOPLLCLKDIV in the subsequent stage will not be in a stable state.

Also, the waveform of CLK_IN is attached.
It was observed by attaching a probe to J1 on the evaluation board, not to the CHIP end.

I would appreciate it if you could give me some advice based on the above.

[keita_yamasaki]

Dear Jing

Thank you for your comment.
We may check it separately, but in that case, thank you.

Best Regards.

[keita_yamasaki]

How about this case?
Customers are in a hurry, and if anything, we would appreciate it if you could teach us.
If you find it difficult to understand, please let us know.

This question is also a question that is also posted to TIC, so once the exchange starts here, I will close it once.

[jingpan]

Hi,

Yes, I can see this phenomenon too. The CLKIN signal seems can't go into AUDIOPLL or bypass AUDIOPLL. But you can select clk_in by CLKOUTSEL0 and CLKOUTSEL1. It can output clk_in to clock output pin.

I can see your question has been given to product team. Please wait.

Regards,

Jing

[Vyssotski]

Dear Jing,

I have a similar problem and could not route CLKIN signal to PLL0 in RT600. I received a very brief answer from technical support that CLKIN can't be used for clock, but it was not explained why. Any thoughts why there is a problem with CLKIN? Is this a chip defect that can;t be fixed in software?

With best regards,

Alexei

[Vyssotski]

Did you succeed in routing CLKIN to PLL in RT600? I had similar problem trying to route 24 MHz from external clock chip to PLL0 in RT600 through CLKIN. I have a guess that it can be a problem of MCUXpresso IDE Clock configurator, but I did not dig into this yet.

[Vyssotski]

I am answering to my own post, hoping that the answer  will be helpful for others, as similar questions were risen earlier.

CLKIN as any input pin needs configuration in Pin Manager. And here automatic selection of "input" when you select CLKIN periphery is not sufficient. One also has to  enable input buffer. The column is named "IBENA" from "Input Buffer Enabled". In the the attached picture correct selection is marked by red oval.

The confusion came partly from non-common name "Input Buffer Enabled". In Cortex-M3, M4 processors of other vendors this selection is called just "Input Enable" ("IE" in CC2650 from TI, and "IN_ENy" in PSoC6 from Cypress Semiconductor). And in more simple 8- and 16-bit processors this register/bit is absent. In MSP430 from TI there is register PxDIR (direction register) that switches off the input buffer automatically when output is selected. And in C8051F and PIC16F processors from Silicon Labs and Microchip respectively, input buffer is switched off only when analog function of the input is selected. With the selection of digital output the input buffer still remains enabled in these 8-bit processors.

With selection IBENA = Enabled input CLKIN works as it should in RT600.