About the 125 MHz (BOARD_BootClockRUN) real frequency

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About the 125 MHz (BOARD_BootClockRUN) real frequency

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LuigiV
Contributor III

I'm using the SAI to interface a Codec, I programmed 32bit, 48000Hz,...instead of a bclk frequency of 3.072MHz I get a 3.125MHz frequency...it seems that the board clock was 127MHz; I choose  the "source frequency" = 125 MHz (BOARD_BootClockRUN).

 

What is wrong ?

 

Thank you.

 

Luigi

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @LuigiV ,

  To this situation, you need to configure the PLL to match your situation.

Eg. you can configure the master clock to : 6.144Mhz.

Then, even it is divided 2, you can get 3.072Mhz

This is the CFG situation with PLL4:

kerryzhou_0-1704964222846.png

 

kerryzhou_1-1704964264032.png

You can check my attached project, mainly the clock_configure.c is used to select the PLL4.

 

Wish it helps you!

Best Regards,

Kerry

 

 

 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @LuigiV ,

  Normally, this is related to your clock configuration.

   You can test your BOARD_BootClockRUN, whether your used freq is really 125Mhz in the code.

   I think, it is related to your clock source issues, you need to make sure the clock source is correct.

  If you still have issues about it, please tell me what the RT chip and board you are using.

Best Regards,

Kerry

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LuigiV
Contributor III

Hi Kerry,

I configured the SAI clock in this way:

 

Source: IPG_CLK_ROOT - BOARD_BootClockRUN: 125 MHz, BOARD_BootClockRUN_400M: 99 MHz

Source Frequency: 125 MHz (BOARD_BootClockRUN)

 

 

This is what I see in the perpherals.h:

 

/***********************************************************************************************************************

* Definitions

**********************************************************************************************************************/

/* Definitions for BOARD_InitPeripherals functional group */

/* NVIC interrupt vector ID (number). */

#define INT_0_IRQN DMA0_IRQn

/* NVIC interrupt handler identifier. */

#define INT_0_IRQHANDLER DMA0_IRQHandler

/* NVIC interrupt vector ID (number). */

#define INT_1_IRQN DMA1_IRQn

/* NVIC interrupt handler identifier. */

#define INT_1_IRQHANDLER DMA1_IRQHandler

/* Definition of peripheral ID */

#define SAI1_PERIPHERAL SAI1

/* SAI1 interrupt vector ID (number). */

#define SAI1_IRQN SAI1_IRQn

/* SAI1 interrupt handler identifier. */

#define SAI1_IRQHANDLER SAI1_IRQHandler

/* Bit clock source frequency used for calculating the bit clock divider in the TxSetBitClockRate function. */

#define SAI1_TX_BCLK_SOURCE_CLOCK_HZ 125000000UL

/* Bit clock source frequency used for calculating the bit clock divider in the RxSetBitClockRate function. */

#define SAI1_RX_BCLK_SOURCE_CLOCK_HZ 125000000UL

/* Sample rate used for calculating the bit clock divider in the TxSetBitClockRate function. */

#define SAI1_TX_SAMPLE_RATE 48000UL

/* Sample rate used for calculating the bit clock divider in the RxSetBitClockRate function. */

#define SAI1_RX_SAMPLE_RATE 48000UL

/* Word width used for calculating the bit clock divider in the TxSetBitClockRate function. */

#define SAI1_TX_WORD_WIDTH 32U

/* Word width used for calculating the bit clock divider in the RxSetBitClockRate function. */

#define SAI1_RX_WORD_WIDTH 32U

/* Number of words within frame used for calculating the bit clock divider in the TxSetBitClockRate function. */

#define SAI1_TX_WORDS_PER_FRAME 2U

/* Number of words within frame used for calculating the bit clock divider in the RxSetBitClockRate function. */

#define SAI1_RX_WORDS_PER_FRAME 2U

/* BOARD_InitPeripherals defines for LPSPI1 */

/* Definition of peripheral ID */

#define LPSPI1_PERIPHERAL LPSPI1

/* Definition of clock source */

#define LPSPI1_CLOCK_FREQ 105600000UL

/* BOARD_InitPeripherals defines for LPI2C1 */

/* Definition of peripheral ID */

#define LPI2C1_PERIPHERAL LPI2C1

/* Definition of clock source */

#define LPI2C1_CLOCK_FREQ 60000000UL

/* Transfer buffer size */

#define LPI2C1_MASTER_BUFFER_SIZE 1

/* Definition of slave address */

#define LPI2C1_MASTER_SLAVE_ADDRESS 0

 

 

Luigi

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @LuigiV ,

  Don't just check the define.

  You can use this related code to get your clock source, and printf it out, give you an example:

#define LPSPI_MASTER_CLK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER + 1U))


Let's test it with code:
    freq_main = LPSPI_MASTER_CLK_FREQ;
    PRINTF("\r\nfreq_main= %d\r\n", freq_main);

 

I mean, you can use the CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk)  to get your clock source, then printf it.

Whether it is the same as your define.

If you still have issues about it.

You can reproduce it in the NXP EVK board, and let me know your used SDK demo, I will help you to check it on my side.

Best Regards,

Kerry

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LuigiV
Contributor III
Thanks Kerry, I inserted your code and I get 60MHz...something is wrong, the bit clock is 3.125MHz instead of 3.072MHz starting by a 125MHz main clock, just a little bit higher...It's not possible that it uses a 60MHz...
Question: why do you start from the CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) to check the SAI clock ?

Luigi
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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @LuigiV ,

  What's the board you are using? I mean, which RT series you are using?

  Then, I will tell you how to check the SAI clock source.

  If you are using the MCUXpresso IDE, you can use the CFG tool to check it.

kerryzhou_0-1704793467817.png

Make sure the clock source freq is correct.

BTW, I have a document for you:

https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/RT10xx-SAI-basic-and-SDCard-wave-file-play/ta-p/...

You can refer to the basic.

 

Wish it helps you!

Best Regards,

Kerry

 

 

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LuigiV
Contributor III

Hi Kerry,

thanks for your support...looking your images I verify the clock frequency; it is 125MHz, but this value can't give me the correct bit clock value of 3.072MHz.

Indeed if I divide the 125MHz by 40, the result is just 3.125MHz for the bit clock and 48.828Khz for the frame clock (these values are what I measure); what I would need is to change the 125MHz to get the right values (as right as possible) for the bit and frame clocks.

 

Luigi

 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @LuigiV ,

  You want to get: 2ch,  32bit, 48000Hz, right?

 Please tell me the RT board and chip you are using, then I will help you generate one correct SAI clock to you.

 Again: Tell me your used RT chip partnumber!!!

 

Best Regards,

kerry

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LuigiV
Contributor III
Hi Kerry,
I'm using the IMXRT1010 EVK.

Thank you, Luigi
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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @LuigiV ,

  To this situation, you need to configure the PLL to match your situation.

Eg. you can configure the master clock to : 6.144Mhz.

Then, even it is divided 2, you can get 3.072Mhz

This is the CFG situation with PLL4:

kerryzhou_0-1704964222846.png

 

kerryzhou_1-1704964264032.png

You can check my attached project, mainly the clock_configure.c is used to select the PLL4.

 

Wish it helps you!

Best Regards,

Kerry

 

 

 

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LuigiV
Contributor III
Thank you Kerry !!
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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @LuigiV ,

  You are always welcome!

  If you still have question about this case, just kindly let me know.

  If your question is solved, please help to mark the correct answer, just to close this case.

  Any new issues, welcome to create the new case or community question post.

 

Best Regards,

Kerry

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