About RT1052 / 1060 SEMC interface conncet SRAM

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About RT1052 / 1060 SEMC interface conncet SRAM

Contributor IV


I did a design recently using a 1062 and had the same questions. I believe that the 1052 will be similar in many respects. What I gathered from the manual and support was this. First thing, most of the important pins are listed in table 49.4.3. For example, WR for SRAM is mapped onto SEMC_ADDR[11]. On the 1060 there is support for a synchronous clock which can be presented at CLKX[0] or CLKX[1]. I don't see this in the 1052 reference manual, so am unsure if you have an option with sync RAM on the 1052.


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NXP TechSupport
NXP TechSupport



  Use table in section 24.4.3 (Pin Mux in SEMC) of the i.MX RT1050 RM and section

24.5.3 (Pin Mux in SEMC) of the i.MX RT1060 for more details about memory signals. 

  Also, customers can refer to app note AN12240 (Enhanced Features in i.MX RT1060)

regarding RT1060 and RT1050 differences. 



Have a great day,




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