ADC_ETC B2B Mode

[mitterha]

Hello,

I have already posted some questions regarding ADC and ADC_ETC in this post but have got no answer so far. Now I have another question.

The RT1020 Reference Manual provides this diagram where I added some information for my question below.

I think the above timing diagram would equal to these settings in MCUXpresso Config Tools:

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Question 1:

Are my following thoughts regarding the signals correct?

• The xbar_trigger comes from the peripheral I chose (PIT_TRIGGER0)
• The xbar_trigger will be internally delayed in the ADC_ETC peripheral and after the Initial delay it will generate an internal signal trigger_req.
• Some other part of the peripheral will receive the trigger_req signal and send the adc_trigger signal to the ADC peripheral. Each pulse on the adc_trigger signal corresponds to one ADC_ETC chain entry for the selected trigger. Therefore after the initial delay the first trigger pulse will start the conversion of chain element #0, the second pulse will start conversion for chain element #1 and so on. Chain elements #3 and #4 will be triggered back2back.

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Question 2:

Is it correct that Chain element #3 has b2b enabled which means "If chain #2 finished the conversion start conversion of chain #3 as soon as possible"?

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Question 3:

Is it correct that the b2b field of Chain #0 has no effect because it is the first chain # which will be triggered and it only waits for the initial delay?

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Question 4:

The Conversion control group can be selected for every chain element. The conversion control group specifies which control register for hardware triggers and which result register (ADCx_HCn & ADCx_Rn) will be used for the conversion.

If I set up my chain element #0 and chain element #4 to use the Conversion control group 0, will the conversion result of chain #4 overwrite the conversion result of chain #0?

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Question 5:

Do I have to set up the Conversion control groups in the ADC peripheral driver with MCUXpresso Config Tools like this

(every Conversion control group with Channel number set to CHANNEL_DRIVEN_BY_ADC_ETC) or will it be enough to initialize the ADC_ETC and the ADC channels will be initialized by the ADC_ETC peripheral?

If I set up the channels like shown above it will result in the warning that there are some duplicated ADC channels in the configuration > the warning suggests that I am doing something wrong here.

Kind regards,

Stefan

[jeremyzhou · Accepted solution]

Hi Stefan Mitterhauser

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.

1) Yes.
2) Yes.
3) Yes.
4) No, the Data in the ADCx_R0 register will be overwritten, but the data for chain elements #0 and #4 will be stored in TRIG0_RESULT_1_0 DATA0 and TRIG0_RESULT_5_4 DATA4 registers.
5) It needs to set up the conversion control groups in the ADC peripheral driver in the MCUXpresso Config Tools.

Have a great day,
TIC

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