A precise data access error has occurred (CFSR.PRECISERR, BFAR) In SDRAM

[Nagaveni]

Hi,

I am using IMXRT1170 board and getting bus fault while running my application with debug log error  A precise data access error has occurred (CFSR.PRECISERR, BFAR) 

please find the below Debug log for information

Wed Sep 27, 2023 12:41:44: IAR Embedded Workbench 9.30.1 (C:\Program Files\IAR Systems\Embedded Workbench 9.1_2\arm\bin\armPROC.dll) 
Wed Sep 27, 2023 12:41:44: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.1_2\arm/config/debugger/NXP/iMXRT_1170.dmac 
Wed Sep 27, 2023 12:41:44: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.1_2\arm/config/debugger/NXP/iMXRT_1170_cm7.dmac 
Wed Sep 27, 2023 12:41:44: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.1_2\arm/config/flashloader/NXP/FlashIMXRT1170_FlexSPI.mac 
Wed Sep 27, 2023 12:41:45: JLINK command: ProjectFile = D:\Git_13092023\TE_01_Baxter_Doppler_Monitor\IMXRT117x_Software\Application\IAR_Project\settings\IAR_Project_flexspi_nor_debug.jlink, return = 0 
Wed Sep 27, 2023 12:41:45: Device "MIMXRT1176XXXA_M7" selected. 
Wed Sep 27, 2023 12:41:45: DLL version: V7.66 , compiled May 18 2022 15:57:48 
Wed Sep 27, 2023 12:41:45: Firmware: J-Link V11 compiled May 23 2023 14:44:38 
Wed Sep 27, 2023 12:41:45: Selecting SWD as current target interface. 
Wed Sep 27, 2023 12:41:45: JTAG speed is initially set to: 32 kHz 
Wed Sep 27, 2023 12:41:45: Found SW-DP with ID 0x6BA02477 
Wed Sep 27, 2023 12:41:45: DPIDR: 0x6BA02477 
Wed Sep 27, 2023 12:41:45: CoreSight SoC-400 or earlier 
Wed Sep 27, 2023 12:41:45: Scanning AP map to find all available APs 
Wed Sep 27, 2023 12:41:45: AP[1]: Stopped AP scan as end of AP map has been reached 
Wed Sep 27, 2023 12:41:45: AP[0]: AHB-AP (IDR: 0x84770001) 
Wed Sep 27, 2023 12:41:45: Iterating through AP map to find AHB-AP to use 
Wed Sep 27, 2023 12:41:46: AP[0]: Core found 
Wed Sep 27, 2023 12:41:46: AP[0]: AHB-AP ROM base: 0xE00FD000 
Wed Sep 27, 2023 12:41:46: CPUID register: 0x411FC272. Implementer code: 0x41 (ARM) 
Wed Sep 27, 2023 12:41:46: Found Cortex-M7 r1p2, Little endian. 
Wed Sep 27, 2023 12:41:46: FPUnit: 8 code (BP) slots and 0 literal slots 
Wed Sep 27, 2023 12:41:46: CoreSight components: 
Wed Sep 27, 2023 12:41:46: ROMTbl[0] @ E00FD000 
Wed Sep 27, 2023 12:41:46: [0][0]: E00FE000 CID B105100D PID 000BB4C8 ROM Table 
Wed Sep 27, 2023 12:41:46: ROMTbl[1] @ E00FE000 
Wed Sep 27, 2023 12:41:46: [1][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table 
Wed Sep 27, 2023 12:41:46: ROMTbl[2] @ E00FF000 
Wed Sep 27, 2023 12:41:46: [2][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7 
Wed Sep 27, 2023 12:41:46: [2][1]: E0001000 CID B105E00D PID 000BB002 DWT 
Wed Sep 27, 2023 12:41:46: [2][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7 
Wed Sep 27, 2023 12:41:46: [2][3]: E0000000 CID B105E00D PID 000BB001 ITM 
Wed Sep 27, 2023 12:41:46: [1][1]: E0041000 CID B105900D PID 001BB975 ETM-M7 
Wed Sep 27, 2023 12:41:46: [1][2]: E0042000 CID B105900D PID 004BB906 CTI 
Wed Sep 27, 2023 12:41:46: [0][1]: E0043000 CID B105900D PID 001BB908 CSTF 
Wed Sep 27, 2023 12:41:46: Cache: Separate I- and D-cache. 
Wed Sep 27, 2023 12:41:46: I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way 
Wed Sep 27, 2023 12:41:46: D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way 
Wed Sep 27, 2023 12:41:46: Reset: Halt core after reset via DEMCR.VC_CORERESET. 
Wed Sep 27, 2023 12:41:46: Reset: Reset device via AIRCR.SYSRESETREQ. 
Wed Sep 27, 2023 12:41:46: AfterResetTarget() start 
Wed Sep 27, 2023 12:41:46: Valid application detected. Setting PC / SP manually. 
Wed Sep 27, 2023 12:41:46:   PC = 0x30007125 
Wed Sep 27, 2023 12:41:46:   SP = 0x20040000 
Wed Sep 27, 2023 12:41:46: Clean & invalidate cached CPU registers 
Wed Sep 27, 2023 12:41:46: AfterResetTarget() end 
Wed Sep 27, 2023 12:41:47: Hardware reset with strategy 0 was performed 
Wed Sep 27, 2023 12:41:47: Initial reset was performed 
Wed Sep 27, 2023 12:41:49: Loaded debugee: C:\Program Files\IAR Systems\Embedded Workbench 9.1_2\arm/config/flashloader/NXP/FlashIMXRT1170_FlexSPI.out 
Wed Sep 27, 2023 12:41:49: Target reset 
Wed Sep 27, 2023 12:42:12: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.1_2\arm/config/flashloader/NXP/FlashIMXRT1170_FlexSPI.mac 
Wed Sep 27, 2023 12:42:12: Downloaded D:\Git_13092023\TE_01_Baxter_Doppler_Monitor\IMXRT117x_Software\Application\IAR_Project\flexspi_nor_debug\lwip_dhcp_usb_freertos.out to flash memory. 
Wed Sep 27, 2023 12:42:12: 849020 bytes downloaded into FLASH (29.17 Kbytes/sec) 
Wed Sep 27, 2023 12:42:12: Loaded macro file: D:\Git_13092023\TE_01_Baxter_Doppler_Monitor\IMXRT117x_Software\Application\IAR_Project/evkmimxrt1170/evkmimxrt1170_connect_cm7.mac 
Wed Sep 27, 2023 12:42:13: FlexRAM configuration is restored 
Wed Sep 27, 2023 12:42:13: SDRAM init done 
Wed Sep 27, 2023 12:42:21: Loaded debugee: D:\Git_13092023\TE_01_Baxter_Doppler_Monitor\IMXRT117x_Software\Application\IAR_Project\flexspi_nor_debug\lwip_dhcp_usb_freertos.out 
Wed Sep 27, 2023 12:42:26: Reset: Halt core after reset via DEMCR.VC_CORERESET. 
Wed Sep 27, 2023 12:42:26: Reset: Reset device via AIRCR.SYSRESETREQ. 
Wed Sep 27, 2023 12:42:26: AfterResetTarget() start 
Wed Sep 27, 2023 12:42:26: Valid application detected. Setting PC / SP manually. 
Wed Sep 27, 2023 12:42:26:   PC = 0x30007125 
Wed Sep 27, 2023 12:42:26:   SP = 0x20040000 
Wed Sep 27, 2023 12:42:26: Clean & invalidate cached CPU registers 
Wed Sep 27, 2023 12:42:26: AfterResetTarget() end 
Wed Sep 27, 2023 12:42:26: Hardware reset with strategy 0 was performed 
Wed Sep 27, 2023 12:42:26: 849020 bytes verified (154.66 Kbytes/sec) 
Wed Sep 27, 2023 12:42:26: Download completed and verification successful. 
Wed Sep 27, 2023 12:42:26: Reset: Halt core after reset via DEMCR.VC_CORERESET. 
Wed Sep 27, 2023 12:42:26: Reset: Reset device via AIRCR.SYSRESETREQ. 
Wed Sep 27, 2023 12:42:26: AfterResetTarget() start 
Wed Sep 27, 2023 12:42:26: Valid application detected. Setting PC / SP manually. 
Wed Sep 27, 2023 12:42:26:   PC = 0x30007125 
Wed Sep 27, 2023 12:42:26:   SP = 0x20040000 
Wed Sep 27, 2023 12:42:26: Clean & invalidate cached CPU registers 
Wed Sep 27, 2023 12:42:26: AfterResetTarget() end 
Wed Sep 27, 2023 12:42:26: Software reset was performed 
Wed Sep 27, 2023 12:42:26: Target reset 
Wed Sep 27, 2023 12:42:47: BusFault exception. 
Wed Sep 27, 2023 12:42:47: A precise data access error has occurred (CFSR.PRECISERR, BFAR) 
Wed Sep 27, 2023 12:42:47: At data address 0x86000000. 
Wed Sep 27, 2023 12:42:47: An imprecise data access error has occurred (CFSR.IMPRECISERR, BFAR) 
Wed Sep 27, 2023 12:42:47: At data address 0x86000000.  
Wed Sep 27, 2023 12:42:47: Exception occurred at PC = 0x301b18a6, LR = 0x301b183b 
Wed Sep 27, 2023 12:42:47: See the call stack for more information. 

This address mentioned in linker file , Please find the attached linker file for More information. Particular __FILE_FIRMWARE_BUFFER__ only facing issue if I remove this application is working properly

please find the preprocessor in command line

__REDLIB__
SKIP_SYSCLK_INIT
CPU_MIMXRT1176DVMAA
CPU_MIMXRT1176DVMAA_cm7
DATA_SECTION_IS_CACHEABLE=1
_DEBUG=1
XIP_EXTERNAL_FLASH=1
XIP_BOOT_HEADER_ENABLE=0
XIP_BOOT_HEADER_DCD_ENABLE=1
USE_RTOS=1
USB_STACK_FREERTOS
PRINTF_ADVANCED_ENABLE=1
SDK_DEBUGCONSOLE=1
SERIAL_PORT_TYPE_UART=1
SDK_OS_FREE_RTOS
MCUXPRESSO_SDK
DEBUG
__USE_CMSIS
CR_INTEGER_PRINTF
PRINTF_FLOAT_ENABLE=1
SERIAL_PORT_TYPE_UART=1
_DLIB_FILE_DESCRIPTOR
USE_SDRAM
SDK_I2C_BASED_COMPONENT_USED
DEBUG_CONSOLE_RX_ENABLE=0
DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
SHELL_NON_BLOCKING_MODE=1
SHELL_HANDLER_ENABLE=1

please let me know where I am missing ?

Thanks In Advance

[kerryzhou]

Hi @Nagaveni ,

  Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.

  From your description, it is related to the SDRAM, please check your used SDRAM, make sure it can support the size upto:0x86000000

As your issue is caused by the 0x86000000.

  Please check it at first.

 BTW, you also can try disable the cache, whether still have issues or not.

Any updated information, please kindly let me know.

Best Regards,

Kerry

[Nagaveni]

Hi kerry, 

Thanks for the response,

1.we are using 1Gbit size of SDRAM with base address of 0x80000000,So there is no issue with address

2. Disabling the cache : 

    .1)Removing DATA_SECTION_IS_CACHEABLE  preprocessor

     2)Making DATA_SECTION_IS_CACHEABLE=0 

     3)by calling the SCB_DisableDCache() function in both SBL and Application

I tried above methods to disable the cache, I am still getting the bus fault (A precise data access error has occurred ). Please let me know is there any other way to disable the cache and mention which cache should I disable.

3. I am using XIP_BOOT_HEADER_DCD_ENABLE=1 preprocessor to initialize the SDRAM in the Bootloader and getting the fault at particular buffer __FILE_FIRMWARE_BUFFER__ . 

please let me know what is the difference between  XIP_BOOT_HEADER_XMCD_ENABLE=1 and XIP_BOOT_HEADER_DCD_ENABLE=0 and which one should I use for SDRAM initialization  along with SBL .

Thanks In Advance

[kerryzhou]

Hi @Nagaveni ,

  Thanks for your updated information.

  Do you test your SDRAM stress or not?

  I mean, check all your SDRAM-related addresses, and make sure all the SDRAM address write and read can pass the stress testing. This is important.

  You can refer to this blog:

https://www.cnblogs.com/henjay724/p/14564390.html

 About your question:XIP_BOOT_HEADER_XMCD_ENABLE=1 and XIP_BOOT_HEADER_DCD_ENABLE=0

In fact, it is two method DCD, one use the XMCD to do the SDRAM initialization, another use the DCD, both method can be used. Your situation is using the XMCD, I think it is OK to use.

You also can try the DCD method, disable the XMCD, whether any improvement or not.

Best Regards,

Kerry

[Nagaveni]

Hi Kerry,
I have already done the stress test and able read and write to the address which I mentioned (present in linker).
I have tested below scenarios.
1) when I do it XIP_BOOT_HEADER_XMCD_ENABLE=1 and XIP_BOOT_HEADER_DCD_ENABLE=0 in the SBL, I am unable to execute the application due to bus faults because of improper initialization of SDRAM.
2) when I tried XIP_BOOT_HEADER_DCD_ENABLE=1 and XIP_BOOT_HEADER_XMCD_ENABLE=0 in the SBL   I am able to execute the application normally, when I added __FILE_FIRMWARE_BUFFER__ = 0x84800000 buffer in the linker unable to execute the application due to bus fault,
Please let me know where it is causing the problem.  

Thanks In Advance

[kerryzhou · Accepted solution]

Hi @Nagaveni ,

   Thanks so much for your information.

   From your description, the XMCD Still lack the SDRAM configuration, but the DCD configuration is completed. The XMCD allows the boot ROM code to configure the SDRAM connected to the SEMCcontroller, it is used to simplify the external RAM enablement.

Please check this PPT which I write:

    To the 0x84800000 buffer, when you test the stress, this address write and read also works, right?

  So, can you do a simple test for this special address, I mean, these address:

0x84800000 buffer, 0x86000000 buffer

  Eg. you use the helloworld in the SDK, add your DCD code, then in the helloworld, to access the 0x84800000 buffer, 0x86000000 buffer, Any issues or not?

  If this method no issues, then your SDRAM totally work, we need to check your app detail situation.

  Please test it, then any updated information, kindly let me know.

Best Regards,

kerry