4bit transfer on LPSPI

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4bit transfer on LPSPI

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david_geng
Contributor I

Further my test to get the maximum throughput form the LPSPI port, I tried to enable the 4bit mode for TX only.

A part from the standard LPSPI test, which I posted in another thread with a nearly working result, I added the following code to enable the 4bit TX transfer.

// enable the 4bit transfer
LPSPI3->TCR &= ~(LPSPI_TCR_TXMSK_MASK); // enable TX
LPSPI3->TCR |= LPSPI_TCR_RXMSK_MASK; // disable RX
LPSPI3->TCR &= ~(LPSPI_TCR_WIDTH_MASK);
LPSPI3->TCR |= LPSPI_TCR_WIDTH(2); // 4bit transfer
// set the pin
LPSPI3->CFGR1 |= LPSPI_CFGR1_PCSCFG(1);

Hey, I can see the data of 4bit on the bus, but there are something does not look very right,

1) in 4bit mode, the clock should only issue 2 pulses, but from the waveform there are 4;

2) the gap (165ns) between each transfer becomes unbearable. PS, should the TX FIFO take care of those gaps?

any idea? thankslpspi_wave3.png 

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jingpan
NXP TechSupport
NXP TechSupport

Hi,

Since I can't find any problem from the code you attached, I made a LPSPI 4-bit demo. It is base on RT1050. But RT1050 and RT1020 are totally same, only different in ram size.

The demo is base on lpspi_interrupt_b2b_master. The waveform seems ok.

tek00000.png

Regards,

Jing

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