1021: CBCMR clock source for SWO & TRACE

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1021: CBCMR clock source for SWO & TRACE

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dmarples
Contributor IV

Hi there,

Could you please confirm the clock section options for bits 15-14 in CBCMR, because setting them to 10 seems to be selecting PLL2 PFD2 rather than PLL2 PFD0 in my configuration...or I've got more sticky fingers with something.

Regards

DAVE

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dmarples
Contributor IV

Hi Jeremy,

I will send you some gdb scripts to do this shortly, but in creating these scripts I've realised that there doesn't appear to be anywhere documented where to set the width of the TRACE bits or, indeed, to switch SWO on - is there a register anywhere where this is done?

I was allowing my J-Trace to do this previously, but I need to be able to do it from gdb with no J-Trace (or similar) in the equation.  On a STM32F4 part this is the register at 0xE0042004 (DBGMCU_CR)...is there an equivalent for this chip?

So, the specific question is; How do switch on (a) SWO and (b) TRACE, with a specified bus width.

Regards

DAVE

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jeremyzhou
NXP Employee
NXP Employee

Hi Dave Marples,

Thanks for your reply.
The ARM_TRACEn pins work with the JTAG port, however, the ARM SWO trace pin works only with the SWD port, obviously, the debug port determinate the kind of trace pin.
About the width of the ARM_TRACEn pins, you can check the value of TPIU_SSPSR (Supported Parallel Port Size Register) for confirmation.

Have a great day,
TIC

 

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dmarples
Contributor IV

Hi there,

I'm aware of the differences, but wanted to know if there was any

configuration location for setting swo and trace output - there is on

stm32, but I don't see anything equivalent documented for RT?

Regards

Dave

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jeremyzhou
NXP Employee
NXP Employee

Hi Dave Marples,

Thanks for your reply.
There's no similar register to select the SWO or JTAG trace feature.

Hope this is clear.

Have a great day,
TIC

 

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jeremyzhou
NXP Employee
NXP Employee

Hi Dave Marples,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) Could you please confirm the clock section options for bits 15-14 in CBCMR
-- The trace clock is derived from the PLL2 PFD0 if TRACE_CLK_SEL bits are 10.

Hope this is clear.

Have a great day,
TIC

 

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dmarples
Contributor IV

Jeremy,

I know this is what the reference manual says, but if I use the clock rate

from PFD0 as the basis for my trace clocks I get the wrong speed out. If I

use PFD2 as the basis of my calculation then I get the correct speeds (with

the TRACE_CLK_SEL bits set to 10). It could be an error in my code, but

could you please confirm that this isn't an error in the manual?

Regards

Dave

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jeremyzhou
NXP Employee
NXP Employee

Hi Dave Marples,

Thanks for your reply.
I was wondering if you can share your demo code and introduce the testing steps, as I'd like to replicate the phenomenon you mentioned.

Have a great day,
TIC

 

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dmarples
Contributor IV

Jeremy,

The easiest way to recreate this is to download the gdbtrace.init script from Orbuculum ( here ) and then run the script below as your .gdbinit. You'll see that with 352000000 (PLL2 PFD0) for the root clock the bitrate at AD_B0_11 is too high, whereas with 396000000 (PLL2 PFD2) it is pretty much exactly correct.  Its _very_ possible I've made a mistake somewhere, but if I have then I don't know where at the moment.

Note that JLink does set the correct divisors but I suspect that's because it's already using PFD2 in its calculation rather then PFD0.

At worst this would be a documentation change, but I would like to get to the bottom of it if possible....it could certainly be something silly I've done.

Regards

DAVE

source ~/Develop/orbuculum/Support/gdbtrace.init
target remote :2331
file targetprogram.elf
set mem inaccessible-by-default off
set print pretty
monitor reset
load

enableIMXRT1021SWO
prepareSWO 352000000 20000000 0 0

dwtSamplePC 1
dwtSyncTap 3
dwtPostTap 1
dwtPostInit 1
dwtPostReset 3
dwtCycEna 1
ITMId 1
ITMGTSFreq 0
ITMTSPrescale 3
ITMTXEna 1
ITMSWOEna 0
ITMSYNCEna 1
ITMEna 1
ITMTER 0 0xFFFFFFFF
ITMTPR 0xFFFFFFFF
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