keil Debug issue for i.MXRT1024 EVK

[srinadh]

Iam using keil v5.34, Debuuger :- CMSIS DAP LINK 2

And i debugging the uart interrupt program, Iam trying send data serial terminal but breakpoints and code debugging not possible it says cant access storage location....

And i send log in command window for keil debug

Please share proper debug options & target options for keil

Running with Code Size Limit: 32K
Include "C:\\Users\\tsrinadh\\Downloads\\lpuart_interrupt_transfer\\lpuart_interrupt_transfer\\evkmimxrt1024\\evkmimxrt1024_sdram_init.ini"
/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

FUNC void SDRAM_WaitIpCmdDone(void)
{
unsigned long reg;
do
{
reg = _RDWORD(0x402F003C);
}while((reg & 0x3) == 0);
}

FUNC void _clock_init(void)
{
unsigned long reg;
// Enable all clocks
_WDWORD(0x400FC068,0xffffffff);
_WDWORD(0x400FC06C,0xffffffff);
_WDWORD(0x400FC070,0xffffffff);
_WDWORD(0x400FC074,0xffffffff);
_WDWORD(0x400FC078,0xffffffff);
_WDWORD(0x400FC07C,0xffffffff);
_WDWORD(0x400FC080,0xffffffff);

// IPG_PODF: 2 divide by 3
_WDWORD(0x400FC014,0x000A8200);
// PERCLK_PODF: 1 divide by 2
_WDWORD(0x400FC01C,0x04900001);
// Enable SYS PLL but keep it bypassed.
_WDWORD(0x400D8030,0x00012001);
do
{
reg = _RDWORD(0x400D8030);
}while((reg & 0x80000000) == 0);
// Disable bypass of SYS PLL
_WDWORD(0x400D8030,0x00002001);

// Ungate SYS PLL PFD2
reg = _RDWORD(0x400D8100);
reg &= ~0x800000;
_WDWORD(0x400D8100,reg);

// SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
// SEMC_CLK_SEL: 1 SEMC_ALT_CLK
// SEMC_PODF: 5 divide by 6
reg = _RDWORD(0x400FC014);
reg &= ~0x700C0;
reg |= 0x50040;
_WDWORD(0x400FC014,reg);

// Disable MPU which will be enabled by ROM to prevent code execution
reg = _RDWORD(0xE000ED94);
reg &= ~0x1;
_WDWORD(0xE000ED94, reg);
}

FUNC void _sdr_Init(void)
{
// Config IOMUX
_WDWORD(0x401F8014, 0x00000000);
_WDWORD(0x401F8018, 0x00000000);
_WDWORD(0x401F801C, 0x00000000);
_WDWORD(0x401F8020, 0x00000000);
_WDWORD(0x401F8024, 0x00000000);
_WDWORD(0x401F8028, 0x00000000);
_WDWORD(0x401F802C, 0x00000000);
_WDWORD(0x401F8030, 0x00000000);
_WDWORD(0x401F8034, 0x00000000);
_WDWORD(0x401F8038, 0x00000000);
_WDWORD(0x401F803C, 0x00000000);
_WDWORD(0x401F8040, 0x00000000);
_WDWORD(0x401F8044, 0x00000000);
_WDWORD(0x401F8048, 0x00000000);
_WDWORD(0x401F804C, 0x00000000);
_WDWORD(0x401F8050, 0x00000000);
_WDWORD(0x401F8054, 0x00000000);
_WDWORD(0x401F8058, 0x00000000);
_WDWORD(0x401F805C, 0x00000000);
_WDWORD(0x401F8060, 0x00000000);
_WDWORD(0x401F8064, 0x00000000);
_WDWORD(0x401F8068, 0x00000000);
_WDWORD(0x401F806C, 0x00000000);
_WDWORD(0x401F8070, 0x00000000);
_WDWORD(0x401F8074, 0x00000000);
_WDWORD(0x401F8078, 0x00000000);
_WDWORD(0x401F807C, 0x00000000);
_WDWORD(0x401F8080, 0x00000000);
_WDWORD(0x401F8084, 0x00000010); // EMC_28, DQS PIN, enable SION
_WDWORD(0x401F8088, 0x00000000);
_WDWORD(0x401F808C, 0x00000000);
_WDWORD(0x401F8090, 0x00000000);
_WDWORD(0x401F8094, 0x00000000);
_WDWORD(0x401F8098, 0x00000000);
_WDWORD(0x401F809C, 0x00000000);
_WDWORD(0x401F80A0, 0x00000000);
_WDWORD(0x401F80A4, 0x00000000);
_WDWORD(0x401F80A8, 0x00000000);
_WDWORD(0x401F80AC, 0x00000000);
_WDWORD(0x401F80B0, 0x00000000);

// PAD ctrl
// drive strength = 0x7 to increase drive strength
// otherwise the data7 bit may fail.
_WDWORD(0x401F8188, 0x000000F1);
_WDWORD(0x401F818C, 0x000000F1);
_WDWORD(0x401F8190, 0x000000F1);
_WDWORD(0x401F8194, 0x000000F1);
_WDWORD(0x401F8198, 0x000000F1);
_WDWORD(0x401F819C, 0x000000F1);
_WDWORD(0x401F81A0, 0x000000F1);
_WDWORD(0x401F81A4, 0x000000F1);
_WDWORD(0x401F81A8, 0x000000F1);
_WDWORD(0x401F81AC, 0x000000F1);
_WDWORD(0x401F81B0, 0x000000F1);
_WDWORD(0x401F81B4, 0x000000F1);
_WDWORD(0x401F81B8, 0x000000F1);
_WDWORD(0x401F81BC, 0x000000F1);
_WDWORD(0x401F81C0, 0x000000F1);
_WDWORD(0x401F81C4, 0x000000F1);
_WDWORD(0x401F81C8, 0x000000F1);
_WDWORD(0x401F81CC, 0x000000F1);
_WDWORD(0x401F81D0, 0x000000F1);
_WDWORD(0x401F81D4, 0x000000F1);
_WDWORD(0x401F81D8, 0x000000F1);
_WDWORD(0x401F81DC, 0x000000F1);
_WDWORD(0x401F81E0, 0x000000F1);
_WDWORD(0x401F81E4, 0x000000F1);
_WDWORD(0x401F81E8, 0x000000F1);
_WDWORD(0x401F81EC, 0x000000F1);
_WDWORD(0x401F81F0, 0x000000F1);
_WDWORD(0x401F81F4, 0x000000F1);
_WDWORD(0x401F81F8, 0x000000F1);
_WDWORD(0x401F81FC, 0x000000F1);
_WDWORD(0x401F8200, 0x000000F1);
_WDWORD(0x401F8204, 0x000000F1);
_WDWORD(0x401F8208, 0x000000F1);
_WDWORD(0x401F820C, 0x000000F1);
_WDWORD(0x401F8210, 0x000000F1);
_WDWORD(0x401F8214, 0x000000F1);
_WDWORD(0x401F8218, 0x000000F1);
_WDWORD(0x401F821C, 0x000000F1);
_WDWORD(0x401F8220, 0x000000F1);
_WDWORD(0x401F8224, 0x000000F1);

// Config SDR Controller Registers/
_WDWORD(0x402F0000,0x10000000); // MCR
_WDWORD(0x402F0008,0x00000081); // BMCR0
_WDWORD(0x402F000C,0x00000081); // BMCR1
_WDWORD(0x402F0010,0x8000001B); // BR0, 32MB
_WDWORD(0x402F0014,0x8200001B); // BR1, 32MB
_WDWORD(0x402F0018,0x8400001B); // BR2, 32MB
_WDWORD(0x402F001C,0x8600001B); // BR3, 32MB
_WDWORD(0x402F0020,0x90000021); // BR4,
_WDWORD(0x402F0024,0xA0000019); // BR5,
_WDWORD(0x402F0028,0xA8000017); // BR6,
_WDWORD(0x402F002C,0xA900001B); // BR7,
_WDWORD(0x402F0030,0x00000021); // BR8,
_WDWORD(0x402F0004,0x000079A8); //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE, SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE.

// _WDWORD(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1
_WDWORD(0x402F0040,0x00000F31); // SDRAMCR0
_WDWORD(0x402F0044,0x00652922); // SDRAMCR1
_WDWORD(0x402F0048,0x00010920); // SDRAMCR2
_WDWORD(0x402F004C,0x50210A09); // SDRAMCR3

_WDWORD(0x402F0080,0x00000021); // DBICR0
_WDWORD(0x402F0084,0x00888888); // DBICR1
_WDWORD(0x402F0094,0x00000002); // IPCR1
_WDWORD(0x402F0098,0x00000000); // IPCR2

_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F00A0,0x00000033); // IPTXDAT
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done.
}

FUNC void restoreFlexRAM(void)
{
unsigned int value;
unsigned int base;

base = 0x400AC000;

value = _RDWORD(base + 0x44);
value &= ~(0xFFFF);
value |= 0x5FA5;
_WDWORD(base + 0x44, value);

value = _RDWORD(base + 0x40);
value |= (1 << 2);
_WDWORD(base + 0x40, value);
}

FUNC void Setup (void) {
SP = _RDWORD(0x00000000); // Setup Stack Pointer
PC = _RDWORD(0x00000004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register
}

FUNC void OnResetExec (void) { // executes upon software RESET
restoreFlexRAM();
_clock_init();
_sdr_Init();
Setup(); // Setup for Running
}

restoreFlexRAM();
_clock_init();
_sdr_Init();

LOAD %L INCREMENTAL // Download

Setup(); // Setup for Running

// g, main
BS \\lpuart_interrupt_transfer\source/lpuart_interrupt_transfer.c\90
BS \\lpuart_interrupt_transfer\source/lpuart_interrupt_transfer.c\112
WS 1, `xfer->data[bytesCurrentReceived]
WS 1, `xfer->data
WS 1, &receiveXfer
WS 1, &sendXfer
WS 1, `xfer
Cannot access Memory (@ 0x04750000, Read, Acc Size: 4 Byte)
Cannot access Memory (@ 0x04750000, Read, Acc Size: 4 Byte)
Cannot access Memory (@ 0x04750000, Read, Acc Size: 4 Byte)
Cannot access Memory (@ 0x04750000, Read, Acc Size: 4 Byte)
Cannot access Memory (@ 0x00c10099, Read, Acc Size: 1 Byte)
Cannot access Memory (@ 0x00c10099, Read, Acc Size: 1 Byte)
Cannot access Memory (@ 0x00c00099, Read, Acc Size: 1 Byte)
Cannot access Memory (@ 0x00c00099, Read, Acc Size: 1 Byte)
Cannot access Memory (@ 0x000c0000, Read, Acc Size: 4 Byte)
Cannot access Memory (@ 0x000c0000, Read, Acc Size: 4 Byte)

[srinadh]

Yeah, But please share TARGET options settings of MIMXRT1024-EVK board

[victorjimenez · Accepted solution]

Hello, 

Please refer to the following community thread. 

i MXRT1024 EVK issue with keil using LPC LINK2 too... - NXP Community

Regards,
Victor