iMXRT1171 - Manual control of the PMIC_ON_REQ pin

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iMXRT1171 - Manual control of the PMIC_ON_REQ pin

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BRK_Y
Contributor III

Hello everyone,

I want to manually control the PMIC_ON_REQ pin, so I’m trying to use the PK_OVERRIDE and PK_EN bits in SNVS->LPCR.

I set the PK_OVERRIDE bit to disable automatic control of the PMIC_ON_REQ pin. Then, I attempted to drive the pin high/low using the PK_EN bit.

PK_OVERRIDE bit   -  1   |   PK_EN bit  -  0  |  Expected Result PMIC_ON_REQ - LOW

PK_OVERRIDE bit   -  1   |   PK_EN bit  -   1  |  Expected Result PMIC_ON_REQ - HIGH

 

However, it didn’t work as expected.

Is there a way to manually control the PMIC_ON_REQ pin?

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mayliu1
NXP Employee
NXP Employee

Hi @BRK_Y ,

Thank you so much for your interest in our products and for using our community.

When SNVS is powered, then PMIC_ON_REQ is  the request signal from SNVS 1P8 to turn on
DCDC, This is controlled internally by the hardware.

mayliu1_0-1761719772612.png

Upon successful power-on, manual control of PMIC_ON_REQ pin may not be practically meaningful.

Because when you set PMIC_ON_REQ low, it will disable DCDC, the result is only SNVS domain is active in the RT1170 chip,  The SoC main domain is completely powered down, and the CPU stops running. 

This is not a normal operation, and we do not recommend you do it.

Wish it helps you.  

Best Regards
MayLiu

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mayliu1
NXP Employee
NXP Employee

Hi @BRK_Y ,

Thank you so much for your interest in our products and for using our community.

When SNVS is powered, then PMIC_ON_REQ is  the request signal from SNVS 1P8 to turn on
DCDC, This is controlled internally by the hardware.

mayliu1_0-1761719772612.png

Upon successful power-on, manual control of PMIC_ON_REQ pin may not be practically meaningful.

Because when you set PMIC_ON_REQ low, it will disable DCDC, the result is only SNVS domain is active in the RT1170 chip,  The SoC main domain is completely powered down, and the CPU stops running. 

This is not a normal operation, and we do not recommend you do it.

Wish it helps you.  

Best Regards
MayLiu

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BRK_Y
Contributor III

@mayliu1 Thank you for your clear explanation.

Actually, here's the issue I'm facing: the wake pin is connected to the INH pin of the CAN transceiver. I'm shutting down the RT1171 using SNVS->LPCR.TOP. After that, I intend to wake the system up via a trigger on the wake pin from the INH signal.

However, the INH pulse sometimes arrives before the RT1171 has fully entered deep sleep, or before the wake flag has been cleared. As a result, this short trigger is missed, and the RT1171 never wakes up.

Is it possible to configure the RT1171 wake pin as level-triggered instead of edge-triggered?

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mayliu1
NXP Employee
NXP Employee

Hi @BRK_Y ,

Thanks for your updated information.

https://www.nxp.com.cn/docs/en/application-note/AN13104.pdf

I suggest you can refer to this Application note, there are more detail description about your question.

mayliu1_0-1761816657148.png

Best Regards

MayLiu

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