iMXRT1062 Slave mode delayed reply to SPI Master

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

iMXRT1062 Slave mode delayed reply to SPI Master

200 Views
bluemax
Contributor I

Hi,
I am testing SPI slave mode (sensor emulation) with Teensy 4.1 (NXP iMXRT1062 )

base on SPISlave_T4* code.

SPI Slave Library for Teensy 4.0/4.1. Contribute to tonton81/SPISlave_T4 development by creating an account on GitHub.
github.com


The SPI master sends CMDx and 0x00 (generate CLK for the SPI Slave reply)
The master transmit sequence is:
CMD1
0x0 //generate CLK for slave reply1
CMD2
0x0 //generate CLK for slave reply2
CMD3
0x0 //generate CLK for slave reply3

At slave code:
SLAVE_TDR = 0x0;
It is done at begin function prior to master command processing.
It is dummy data, that populate initial TX slot.
The result of the Slave processing :

Master                                  Slave
------------------------------------------
Master_CMD1                      0x0 <---- since the begin operastion loaded the TX slot
0x0                                           0xFF <---- since the code did not process Master_CMD1 YET!!!!

                                                                no TX from slave
Master_CMD2                     Slave_Reply_for_CMD1 <----- after Master_CMD1 was processed!!!

                                              IT IS IN DELAY! OF 1 BYTE 1 !!!
0x0                                              0x0 <--- each slave TX is followed by TX of 0x0

Can anyone provide some idea why the late delay of Master incoming data processing?

Teensy is at 600Mhz and SPI is at 8Mhz

Please note : 
if i prepare 2 values for the first command prior to getting CMD it work fine
Master                                 Slave
------------------------------------------
Master_CMD1                     Slave_Reply1_default
0x0                                          Slave_Reply2_dafault
Master_CMD2                   Slave_Reply_for_CMD1

its looks like the SPI Slave processing of the Master Commands is done in 16 CLK shift.



Thanks for the help

Tags (3)
0 Kudos
Reply
0 Replies