Hope you are doing well.
If you divide the three sections and place non-cacheable region, it can avoid the cache data coherency problem. But the side-effect is the performance of accessing the buffer is not good as cacheable ones if CPU access them multiple times. So it is expected that the performance drops.
Maybe I misunderstood your questions, but could you please describe what is the main objective that you would like to achieve with these regions.
Best Regards,
Sabina
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