iMX RT1062 SDK LCD clocking

[mspenard603]

I'm using NXP's iMX RT1062 eval kit with the Rocktech 4" LCD. I have a SDK question related to the fsl_elcdif example code. Specifically how the LCD gets clocked. 

Why do your comment say 93Mhz for PLL clock rate when the Rocktech display runs at 9.3Mhz. Why the factor of 10?

Here's your full comments:

void BOARD_InitLcdifPixelClock(void)
{

    /*
     * The desired output frame rate is 60Hz. So the pixel clock frequency [for RockTech] is:
     * (480 + 41 + 4 + 18) * (272 + 10 + 4 + 2) * 60 = 9.2M.
     * Here set the LCDIF pixel clock to 9.3M.
     */

    /*
     * Initialize the Video PLL.
     * Video PLL output clock is OSC24M * (loopDivider + (denominator / numerator)) / postDivider = 93MHz.
     */

   clock_video_pll_config_t config = {
           .loopDivider = 31, .postDivider = 8, .numerator = 0, .denominator = 0,
       };  
    CLOCK_InitVideoPll(&config);

..

}

Your first comment block spells out the math behind and goal of 9.3mhz (which is the LCD's sync rate). But then your PLL code states the goal is 93mhz. So why the factor of 10 increase?

[Hui_Ma · Accepted solution]

Hi,

The first calculated 9.2MHz clock frequency is LCD pixel clock frequency.
The eLCDIF clock source from PLL5, which clock source is 24MHz.
It doesn't need to enlarge fixed to 10 times with 93MHz of PLL5 output clock.
I just use MCUXpresso config tool to let PLL5 output clock frequency with 186MHz.
Then it also could get 9.3MHz LCD pixel clock.

Please check below picture for the detailed info:

The related code should be:

void BOARD_InitLcdifPixelClock(void)
{
    /*
     * The desired output frame rate is 60Hz. So the pixel clock frequency is:
     * (480 + 41 + 4 + 18) * (272 + 10 + 4 + 2) * 60 = 9.2M.
     * Here set the LCDIF pixel clock to 9.3M.
     */

    /*
     * Initialize the Video PLL.
     * Video PLL output clock is OSC24M * (loopDivider + (denominator / numerator)) / postDivider = 186MHz.
     */
    clock_video_pll_config_t config = {
        .loopDivider = 31, .postDivider = 4, .numerator = 0, .denominator = 0,
    };

    CLOCK_InitVideoPll(&config);

    /*
     * 000 derive clock from PLL2
     * 001 derive clock from PLL3 PFD3
     * 010 derive clock from PLL5
     * 011 derive clock from PLL2 PFD0
     * 100 derive clock from PLL2 PFD1
     * 101 derive clock from PLL3 PFD1
     */
    CLOCK_SetMux(kCLOCK_LcdifPreMux, 2);

    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 4);

    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
}

Wish it helps.

Have a great day,
Mike

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

[mspenard603]

I see. So there are 2 stages of scaling. I missed the CLOCK_x(); statements thinking they only set the mux.

 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 4);

 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);