iMX.RT1050 - DCDC fast reset failure

[WagnerMSP]

Hello, NXP team!

We are designing a board with the i.MXRT1051. We already have the first prototype.

Unfortunately, we found an issue. When the main power on the board is turned off and turned on fast enough, the MCU will get stuck. I have concluded that the issue is caused by the power-up sequence not being followed correctly.

The DCDC_PSWITCH is controlled by an RC circuit, exactly like on the EVK. I have identified that when the main power reset is fast enough, the DCDC_PSWITCH will not be delayed by the minimum 1ms required causing the DCDC_OUT to not be turned on properly.

I've found another posts about this issue, but no definitive solution.

My main question is:

What would be the way to prevent this issue from happening, considering I can't guarantee a perfect voltage supply in the field? I don't mind resetting the MCU, but it can not get stuck.

Can a voltage supervisor be used to control the DCDC_PSWITCH? Considering we are using the APX803S-26SA-7 (2,63V 240ms) for the PORB port, could we use the  APX803S05-26SA-7(2,63V 50ms) on the DCDC_PSWITCH port?

[Omar_Anguiano]

Hello
I hope you are well.

Yes, a voltage monitor is a suitable solution for this issue.
We utilize voltage monitor circuit with delayed reset output (e.g. like UM805RE). This circuit monitors the main RT1xxx 3.3V power supply voltage (external 5V to 3.3V DCDC). When output voltage falls below 2.63V (RE in device UM805) it generates a reset signal (in our case it pulling reset output low) for specific delay (this delay must be considered enough to discharge capacitance across DCDC_PSWITCH, it means the voltage at DCDC_PSWITCH must go below 0.5V during this delay time). The reset output of this voltage monitor is connected to enable input of external DCDC, it means DCDC 3.3V output is disabled during whole reset delay interval. During this interval it must be achieved that DCDC_PSWITCH will go below 0.5V.

Best regards,
Omar

[WagnerMSP]

Hello, Omar.

Thank you for helping me.

Regarding the circuit you proposed, wouldn't the voltage monitor disable the power supply that supplies itself? After the voltage monitor disabled the external DCDC, how would it be enabled again if the voltage monitor itself is not supplied anymore?

What I was planning was to use the voltage monitor controlling the DCDC_PSWITCH directly, as below:

Do you think that this circuit would work?

Best regards,

Wagner

[Omar_Anguiano]

These devices perform a single function: They assert a reset signal whenever the VCC supply voltage falls below a preset threshold, keeping it asserted for at least some ms after VCC has risen above the reset threshold.

I don’t recommend your circuit since you also have to comply with the power-up sequence.  The total RC for PSWITCH delay should be 5-15 ms. This reset from the voltage monitor should be to the enable signal of the power source so when this happens. It will give enough time for the capacitor to discharge before the power-up sequence.

Best regards,
Omar