What is highest achievable sample rate for USB Audio 2.0 device using i.MXRT1011/i.MXRT1021 ?

[paulw2]

Hi,

I'm trying to determine whether it is possible/practical/reliable for UAC2 audio device implementations on i.MXRT1011 and i.MXRT1021 using SAI or FlexIO to achieve sample rates of >= 768 kHz.

I recall reading a document some time back, which I can't find right now, that described techniques to achieve higher sample rates, >= 768 kHz, using 2 SAI's if I recall correctly.

Any pointers to techniques, and/or documents describing how to achieve higher sample rates, including for DSD, would be greatly appreciated.

Thanks in advance,

Paul.

[Habib_MS]

Hello @paulw2,

Unfortunately, SAI does not support 786kHz sampling rate, this is because the maximum BCLK supported by the i.MX RT1xxx series is 25MHz. Also, FlexIO only supports a maximum sample frequency of 96kHz.

On the other hand, I did not find anything related to using 2 SAIs to reach 768kHz. Can you give me more information about this?

Sorry for the inconvenience this may cause.

BR
Habib.

[paulw2]

Hi @Habib_MS,

Thanks for your reply.

The SAI figure you've provided ties in with the document sources I've located.

https://www.nxp.com/docs/en/data-sheet/IMXRT1050CEC.pdf

Pg 57 - Table 51 Master Mode SAI timing

SAI_MCLK cycle time - min (max speed) - 15nS - 66.66 MHz
SAI_BCLK cycle time - min (max speed) - 40nS - 25 MHz

How is the FlexIO sample rate you've listed derived ?

i.MXRT1020 Processor Reference Manual - Table 14-5 System Clock Frequency values

SAI1_CLK_ROOT 66MHz
FLEXIO1_CLK_ROOT 120MHz - note comment below, so divide by 4 = 30MHz

https://www.nxp.com/docs/en/supporting-information/FTF-ACC-F1179_Introduction_to_FlexIO.pdf

I2S Master :-
Due to synchronization delays, the setup time for the receiver input
is 1.5 FlexIO clock cycles, so the maximum baud rate is divide by 4
of the FlexIO clock frequency

I'm still hoping for info from someone who knows of techniques to work around these limitations.

I don't have the reference document for using 2 SAI's, I was hoping someone in the community might know of this approach and/or document.

Thanks and regards,

Paul.

[paulw2]

Hi @Habib_MS,

Do you, or anyone else, know what is meant by the SAI MCLK part of the following comment in the sai1 stanza nxp_rt10xx.dtsi in Zephyr ?

Especially in light of the limitations highlighted earlier in this thread.

/* The maximum input frequency into the SAI mclk input is 300MHz
 * Based on this requirement, pre-div must be at least 3
 * The pre-div and post-div are one less than the actual divide-by amount.
 * A pre-div value of 0x1 results in a pre-divider of
 * (1+1) = 2
 */

Thanks and regards,

Paul.

[Habib_MS · Accepted solution]

Hello @paulw2 ,
For  FlexIO sampling rate, the internal team did some testing, and this is the maximum sampling rate of FlexIO. Although FlexIO could be faster, there is no guarantee that it will run without issues.

In the other hand, the reason for that comment may be because it is using the PLL4 as a clock source, where its frequency is 786.43 MHz, so in order to meet the maximum input frequency into the SAI mclk, pre-div must be at least 3.
The formula that is currently used to configure a pre divider value is the next: (value + 1). Following the example in the comment:
A pre-div value of 0x1 results in a pre-divider of: (1+1) = 2
This also is used in the SDK (version 2.16) function called "CLOCK_SetDiv", as shown the next image:

BR
Habib

[paulw2]

Thanks very much for following this up @Habib_MS 

Best regards,

Paul.