What is happening here at startup?

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What is happening here at startup?

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CktDesigner
Contributor IV

I'm using the MIMXRT1060-EVKB in preparation for creating a custom board.

I'm also using MCUXpresso with version 2.13.0 of the SDK.

My application was working, then stopped working.    I couldn't even get the debugger to work properly.

My final application will boot from SDcard into I/D TCM and run.    I made the appropriate modifications, to the onchip SRAM setup in MCUXpresso, and added code to ResetISR to properly map the onchip SRAM banks.

This was all working, but suddenly stopped working.

I set a breakpoint at ResetISR, then stepped through the instructions until I saw an issue.

Image "After_0x2338" shows the registers, etc. after executing the instruction at 0x2338.   It shows the correct value in R0 and the incremented PC.

Image "After_0x233A" shows the machine state after the next instruction.  Here you can see that R1 has the expected value and the incremented PC.

Image "After_0x233C" shows the machine state after the next instruction.  The PC has been incremented, but the memory has changed.   It now appears that it is filled with "Text" and the instructions that follow are corrupted.

The way I understand things, the "STR R1, [R0]" instruction is writing the onchip SRAM configuration register, but it shouldn't take effect until the write to 0x400ac040 occurs.  

Since I'm "loading" to ITCM, then changing the ITCM mapping, I was careful to keep the ITCM banks that were loaded during boot (and not re-map them).

As I said, this all worked before...  

Any suggestions on what happened?

Thanks!

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CktDesigner
Contributor IV

Evidently bit 2 of the register controlling where to read the on-chip configuration doesn't clear on reset, so the configuration is being read from the software writable on-chip configuration.   So as soon as the configuration register is written, the mapping occurs...       Adding code to clear that bit before writing the configuration register, then setting the bit again gets the expected behavior...

But the underlying problem is trying to boot to ITCM while also trying to change the configuration of the on-chip SRAM.     Still trying to figure out how to configure the on-chip SRAM and boot from SDcard in a system that doesn't have external Flash...

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CktDesigner
Contributor IV

Evidently bit 2 of the register controlling where to read the on-chip configuration doesn't clear on reset, so the configuration is being read from the software writable on-chip configuration.   So as soon as the configuration register is written, the mapping occurs...       Adding code to clear that bit before writing the configuration register, then setting the bit again gets the expected behavior...

But the underlying problem is trying to boot to ITCM while also trying to change the configuration of the on-chip SRAM.     Still trying to figure out how to configure the on-chip SRAM and boot from SDcard in a system that doesn't have external Flash...

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