Using both FlexSPI as masters for external traditional SPI devices with i.MXRT 106x (or other)

[functional_des]

Hello,

We are in need of a device that can take in Ethernet data, and control an array of SPI devices operating at 50Mbps. From what I can tell, it looks like the i.MX 1060x chips could be a good fit for this. Given our timing constraints our optimal configuration would be to split our SPI chip array in two, allowing us to write to our array roughly twice as fast. From what I can tell we should be able to control those two arrays on separate FlexSPI ports. However it seems that this is not really what the FlexSPI is meant for, and so I want to clarify a few things: 

1. Can the FlexSPI be used as a 50Mbps SPI Master to control a traditional SPI device (single MOSI/MISO)? I am quite confident the answer is yes, but I may as well confirm since I'm here.
2. Is it possible to actually use both FlexSPI ports as I'm imagining, or is there some limitation that I'm not expecting? My main concern is that it seems like the main use case for the FlexSPI ports is to access off-chip memory. In my case though I would prefer to boot from onboard memory, and use both FlexSPI ports. Is that possible? 
3. Is there some better way to do this that I am not considering? From what I can tell the LPSPI is not sufficient for our use case. But it seems like perhaps FlexIO could be a viable way to do this- It looks like a viable path I could do there is to use the 480MHz USB PLL, and then Prescale it by 10 to get a 48Mbps clock. If that is the case, then presumably I could move to a chip that has fast FlexIO and does not need to have 2xFlexSPI ports? 

Thanks

[jeremyzhou · Accepted solution]

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) Can the FlexSPI be used as a 50Mbps SPI Master to control a traditional SPI device (single MOSI/MISO)? I am quite confident the answer is yes, but I may as well confirm since I'm here.
-- Yes.
2) Is it possible to actually use both FlexSPI ports as I'm imagining, or is there some limitation that I'm not expecting? My main concern is that it seems like the main use case for the FlexSPI ports is to access off-chip memory. In my case though I would prefer to boot from onboard memory, and use both FlexSPI ports. Is that possible?
-- It's possible to use multi FlexSPI ports simultaneously.

3) Is there some better way to do this that I am not considering? From what I can tell the LPSPI is not sufficient for our use case. But it seems like perhaps FlexIO could be a viable way to do this- It looks like a viable path I could do there is to use the 480MHz USB PLL, and then Prescale it by 10 to get a 48Mbps clock. If that is the case, then presumably I could move to a chip that has fast FlexIO and does not need to have 2xFlexSPI ports?
-- In my opinion, the FlexSPI is too hard to implement your purpose, as it's restricted to following the sequences in the LUT to drive the signals and the LUT only supports the sequences that are related to the memory chips.
So I think the FlexIO is the option.

Have a great day,
TIC

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