UFL RT added to jlink probe to flash rt600 still have issues.

[skanda19]

Hello I been following the series to setup the external flash through flexspi. So far with SPT i been able to flash the memory, but I need to get it done also with mcu xpresso IDE entirely. 

I've added already the UFL RT algorithm to my folders and is the algorithm use when I try to flash it, as you can see from my screenshot of the console: 

the LUT and FCB I got them from the python code provided in this application note https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs-Knowledge/i-MX-RT-FLEXSPI-booting-guide/ta-p/166... didn't work, but also with the one I have created is giving me the same issue, I think i added all the lut functions needed for this to work (both files attached). 

In some other notes, I remember reading about enabling in octal mode, but seems like the .xml already accounts for this:

 

any suggestions ?

[mayliu1]

Hi @skanda19 ,

Thank you so much for your interest in our products and for using our community.

Could you let me know whether you are using an NXP development board or a customized board? What is the flash type, and what are the boot mode and ISP pin configurations?

 

The FCB settings are closely related to the flash type and need to be configured according to the specific flash  characteristics

Wish it helps you.
If you still have question about it, please kindly let me know.

Wish you a nice day!

Best Regards
MayLiu

[skanda19]

Hello @mayliu1,

Is a custom evk, we are interfacing with the issi NOR type flash is25wx256-jhle in octal DDR mode booting from flexspi A. 

My main goal is to first get rid of the use of secure provisioning tool for this and only use mcu xpresso, seems to be easier to use jlink flash than a nxp mcu link / cmsis-dap probe. 

At the moment, I know how to load the program into memory flash using the external tools, and also have implemented a partial driver for in-application ops that allows me to Erase the entire chip in Octal DDR mode at 200MHz. 

Meaning my configuration for flexspi works, and also have a lut (thaht might need some work still).

Now,  I want to know if the order in which the operations of the LUT has to be in a certain order ? 

And then those the RT-UFL algorithm need any other mods to the scripts or the JLinkDevices.xml ? (Contained in:RT-UFL1.0.zip) reference: https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs-Knowledge/RT1170-Octal-flash-enablement/ta-p/149... chapter 5
 

Thanks for your help!

[mayliu1 · Accepted solution]

Hi @skanda19 ,

Thanks for your updated information.

Regarding your question, I suggest you can refer to this link which wrote by an IMXRT expert.

痞子衡嵌入式：从头开始认识i.MXRT启动头FDCB里的lookupTable-CSDN博客

I've translated a portion of this document into English for you ：

" the application is booted by the BootROM, which has its own set of configuration rules for FlexSPI.  It rigidly fixe  the position of CMD_LUT_SEQ_IDX_READ, meaning the read access sequence must be the first sequence in FlexSPI->LUT[],   because BootROM configures FlexSPI->FLSHxCR2[ARDSEQID] to 0. Therefore, when prepare the FDCB, then the first sequence in the lookup table must be allocated for the read access sequence."

For your second question:

Please refer to this link.  https://www.cnblogs.com/henjay724/p/14942574.html

Best Regards
MayLiu

[skanda19]

Hello @mayliu1,


Thanks for you support and effort to try help sort this out, turns out this Monday was able to determine the order of the LUT cmds and finally my bootheader works! 

thanks again, and I will mark this as the solution for this thread! thanks May!

[mayliu1]

Hi @skanda19 ,

You are welcome.

I'm glad your issue has been resolved, and I appreciate your recognition of my work.

Best Regards

MayLiu