Termination of unused IOs pins in IMXRT500

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Termination of unused IOs pins in IMXRT500

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Saleh_94
Contributor I

Hi there, 

 

In the technical Datasheet, it was mentioned there in the Termination of Unused IO pins Title that all high-speed PIOn pins if not used should be pulled internally or externally to the ground. so, my question is which pins are considered high-speed pins and which are not? also what are the pins that should be pulled down externally, and What is the effect that will happen if lifted floating? keeping in mind that I am using the FOWLP249 package. 

Saleh_Aleid_94_0-1719925617346.png

also it was mention in the note 2 that these pins also should be pulled down internally from the software side, are they same as the previous picture or extra. 

Saleh_Aleid_94_1-1719926085591.png

 

 

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Habib_MS
NXP Employee
NXP Employee

Hello @Saleh_94,

The RT595 provide two GPIO architectures, where are called pads in the RM.

These pads are called Fail Safe and high Speed, in addition, the main difference in the structure of these two pads is that the High-Speed pads have diodes to VDD and VSS, while the Fail-Safe pads only have diodes to VSS. As mentioned in the chapter 12 called "IO PAD Controller (IOPCTL)" in the RM. If you need more information about the architecture, you can consult the mentioned chapter.   

Also, in the next images shows the architectures of all GPIO pins that were obtained in the chapter 1.5 called "Power supply for pins" in the datasheet:

Habib_MS_0-1720215602070.png

 

Habib_MS_1-1720215602072.png

Also, if you experience any issue, do not hesitate to let me know.

BR

Habib.

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4,203 次查看
Habib_MS
NXP Employee
NXP Employee

Hello @Saleh_94,

The RT595 provide two GPIO architectures, where are called pads in the RM.

These pads are called Fail Safe and high Speed, in addition, the main difference in the structure of these two pads is that the High-Speed pads have diodes to VDD and VSS, while the Fail-Safe pads only have diodes to VSS. As mentioned in the chapter 12 called "IO PAD Controller (IOPCTL)" in the RM. If you need more information about the architecture, you can consult the mentioned chapter.   

Also, in the next images shows the architectures of all GPIO pins that were obtained in the chapter 1.5 called "Power supply for pins" in the datasheet:

Habib_MS_0-1720215602070.png

 

Habib_MS_1-1720215602072.png

Also, if you experience any issue, do not hesitate to let me know.

BR

Habib.

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