Teensy 4.1 DMA Hardware Chain Issue: 4:1 PIT Trigger to ADC_ETC Trigger Ratio

[RhodesLover]

Hello everyone,

I'm encountering a persistent issue with a hardware chain setup on a Teensy 4.1 (IMXRT1062) and would greatly appreciate any insights. My goal is to achieve a 1:1:1 trigger ratio across the following chain: PIT Timer -> XBAR -> ADC_ETC -> ADC1 -> DMAMUX -> DMA

Problem: Despite various debugging attempts, I consistently observe a 4:1 ratio between the PIT Timer ISR count and the ADC_ETC ISR count. For every 4 PIT interrupts, I get only 1 ADC_ETC interrupt. 

Current Setup:

- PIT Timer (Channel 0): Configured to trigger at 100 Hz (10ms period). Its interrupt is enabled for debugging purposes.
- XBAR: PIT Timer 0 output (XBARA1_IN_PIT_TRIGGER0 => SEL51) is routed to XBARA1_OUT_ADC_ETC_TRIG00 (Output 103).
- ADC_ETC: Configured to be triggered by TRIG0 (which corresponds to XBARA1_OUT_ADC_ETC_TRIG00). DMA_MODE_SEL is enabled, TRIG0_ENABLE is set, PRE_DIVIDER is 0, TRIG_CHAIN length is 1, B2B0 is enabled, HWTS0 is set to ADC TRIG0 (bit 0), and CSEL0 is set to ADC Channel 1.
- ADC1: Configured for fast conversion on Channel 1. Calibration is attempted (and expected to fail with fast settings).
- DMA (Channel 16): DMAMUX source is ADC_ETC (source 23). DMA is set up to transfer data from ADC_ETC_TRIG0_RESULT_1_0 to a global buffer, with an interrupt on major loop completion.

Observed Output (Example after 3 seconds):

FULL HARDWARE CHAIN TEST
PIT -> XBAR -> ADC_ETC -> ADC1 -> DMAMUX -> DMA
================================================================================
Starting Hardware Setup...
Configuring PIT Timer for 10000 us period...
PIT_LDVAL0 set to: 1499999 (for 10000 us at F_BUS = 150000000 Hz)
PIT Timer configured (with debug interrupt, but not yet started).
Configuring XBAR (PIT0 -> ADC_ETC_TRIG00)...
XBARA1_SEL51 AFTER: 0x3800 (Input 56 written for Output 103)
Configuring ADC1 for Hardware Chain...
ADC1_CFG set to fast: 0x00002000
ADC1_HC0 for Channel 1: 0x00000001
Starting ADC1 calibration (expected to fail with CFG=0x2000)...
Calibration failed (CALF=1) - as expected for this CFG test.
ADC1_GC final: 0x00000000 (Expected: 0x00000000, since ADC_ETC handles DMA)
ADC1_GS final: 0x00000001 (ADACT should be 0, CALF should be 1)
ADC1 configured for Hardware Chain.
Configuring ADC_ETC for Hardware Chain (waiting for ADC1)...
ADC_ETC_CTRL: 0x20000001
ADC_ETC_TRIG0_CTRL: 0x00000000
XBARA1_OUT_ADC_ETC_TRIG00 = 103 (0x67)
ADC_ETC_TRIG0_CHAIN_1_0 (set directly to 0x3002): 0x00003002
DEBUG: ADC_ETC_TRIG0_COUNTER: 0x00000000
ADC_ETC_DMA_CTRL (enabled): 0x00000001
ADC_ETC configured for Hardware Chain.
Configuring Channel 16 for DMA (ADC_ETC triggered)...
DMAMUX_CHCFG16 configured for ADC_ETC (Source 23): 0x00000017
DIRECTLY AFTER CSR ASSIGNMENT: DMA_TCD16_CSR SHOULD BE 0x0002, IS: 0x0002
AFTER DMA_SERQ=16 -> DMA_TCD16_CSR: 0x0002
AFTER DMA_SERQ=16 -> DMA_ERQ: 0x00010000 (Bit 16 should be 1)
Channel 16 for ADC_ETC-DMA configured.
Hardware Setup Complete

--- REGISTER BASELINE: After full setup ---
ADC_ETC_CTRL: 0x20000001
ADC_ETC_TRIG0_CTRL: 0x00000000
ADC_ETC_TRIG0_COUNTER: 0x00000000
ADC_ETC_TRIG0_CHAIN_1_0: 0x00003002
ADC_ETC_TRIG0_RESULT_1_0: 0x00000000
ADC1_GS: 0x00000001
ADC1_HC0: 0x00000001
--- END REGISTER BASELINE ---
Starting Hardware Chain...

Monitoring (3 Seconds):
Time | PIT ISR | ADC_ETC ISR | DMA ISR
------------------------------------------
0s | 32 | 8 | 8
0s | 64 | 16 | 16
0s | 96 | 24 | 24
1s | 128 | 32 | 32
1s | 160 | 40 | 40
1s | 192 | 48 | 48
2s | 224 | 56 | 56
2s | 256 | 64 | 64
2s | 288 | 72 | 72
3s | 320 | 80 | 80
ADC_ETC TRIG0 Error Count: 0
ADC1_GS at last ADC_ETC ISR: 0x00000001
WARNING: ADC1 was active at least once upon entering ADC_ETC ISR!
DMA Error Status (DMA_ES): 0x00000000
DMA Channel 16 CSR (DMA_TCD16_CSR): 0x0002
DMA Channel 16 Interrupts (dma_ch16_actual_isr_count): 80
================================================================================

Result:
PIT Interrupts: 320 (expected: ~300)
ADC_ETC Interrupts: 80 (expected: ~300)
DMA Interrupts: 80 (expected: ~300)
Hardware Chain Problem
The expected 1:1:1 ratio was not achieved.
================================================================================

Attempts Made & Observations:

- Verified XBAR routing from PIT to ADC_ETC.
- Ensured ADC_ETC_CTRL has PRE_DIVIDER=0 and TRIG0_ENABLE=1.
- Set ADC_ETC_TRIG0_CHAIN_1_0 with IE0=1, B2B0=1, HWTS0=ADC TRIG0 (bit 0), and CSEL0=1.
- Set PIT ISR priority to 0 (highest) and DMA ISR priority to 1.
- Temporarily disabled the PIT ISR to check if it interfered with XBAR triggering (no change in behavior).

The core problem remains the 4:1 ratio between PIT and ADC_ETC interrupts.

Any suggestions on what might cause this consistent 4:1 ratio.

Thank you in advance for your help.

I've attached the code.
You can compile and check by yourself by entering "hwchain" in the terminal.

Thanks,
Chris

[Gavin_Jia]

Hi @RhodesLover ,

Thanks for your interest in NXP MIMXRT series!

I extended the EDMA functionality based on the example(adc_etc_hardware_trigger_conv) in the SDK, which I tested locally with no problems, so you can try it out.

Best regards,
Gavin