STRH instruction causing unaligned memory access fault on i.MXRT1062

[odd_bikes]

As per the title says, I have an IMXRT1060 and getting an unaligned access fault due to an STRH instruction. The odd thing is that the Cortex-M7 manual explicitly mentions that unaligned access are accepted for certain instructions, STRH being one of them.

strh r7, [r0, #4]

I've attached screenshots of the registers before this line (to see that R0 points to an unaligned address in RAM) and also with the state of the the fault system configuration (unaligned traps are disabled).

[gobbo]

Strangely enough, I'm having the same issue... the memory region is set to 

    MPU->RBAR = ARM_MPU_RBAR(7, 0x20240000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB);

but my trap seem to happen at 0x2030_001D  -- the address is indeed unaligned, but i suppose that should be OK in this instance.

[DanielRuvalcaba]

Hi,

I’m sorry for the late response.

Did you modified any memory configuration?

Are you using a custom board?

Could you please share with me the code you execute to trigger this fault?

Best regards, Daniel.  

[odd_bikes]

Is there a chance that NXP didn't add support for unaligned memory access, as it is described in ARM's Cortex-M7 technical reference manual?

[gobbo]

You don't happen to be accessing OCRAM2 with this instruction?