Dear All,
Does the NOR interface behave the same as the SRAM interface with respect to “set SRAM base address as 0xA000_0000 to avoid this behavior” ?
And does it happen in 8bit data widht mode?
BR,
George
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Hi George,
It is not about SEMC, it is up to ARM arch, so PRAM interface should have the same limitation, and for PNOR, it doesn't support AXI write.
Best Regards,
Jay
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What kind of NOR do you mean? Parallel NOR over SEMC or Serial NOR over FlexSPI?
Dear jayheng,
Thank you for your reply.
My concern is that using the parallel NOR interface via SEMC generates four bus cycles similar to the post described above.
Does this occur in either Psedo-RAM mode or Parallel NOR mode?
