SPI via DMA - gap between words.

[cerma]

Hi,

I'm using SPI over DMA. Transfer functions properly. One DMA transfer is 400 bytes (200x16bit). PCS is controlled by my code. After the first word, the gap is 20us. Among other words, there is a 2.4us gap. Does anyone know why? How to eliminate the gap?
The SPI DMA settings are attached. PrintScreen SPI is attached (CLK - green, MOSI - pink, PCS - blue).

I´m using custom PCB with i.MX1061, MCUXpresso11.2, SDK2.8.0 Manifest Ver 3.6.0, BareMetal, Win10.

Best Regards,

Jaroslav C.

[Alexis_A]

Hello @cerma,

The delay between transfer is the parameter that manages this gap, but the strange thing is that any of this gap corresponds to the one you set and there's a difference between the delays.

Does this always happen at the start of the transmission? 

If you do not use the DMA, the behavior is the same?

Best Regards,

Alexis Andalon

[cerma]

Hi alexis,

I've already tried to change this setting. The result did not match set values. ...

When I set 0 everywhere, the gap is 0. But there is still a gap of 54.8us between the first and second word. I do not know why.

Best Regards,

Jaroslav

[Alexis_A]

Hello @cerma, 

Could you try looking at the code generated by the tool? By default this is set to the following values:

masterConfig->pcsToSckDelayInNanoSec = 1000000000U / masterConfig->baudRate * 2U;
masterConfig->lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig->baudRate * 2U;
masterConfig->betweenTransferDelayInNanoSec = 1000000000U / masterConfig->baudRate * 2U;

Also, are you setting this using a EVK, or is a custom board? Which device are you using as a slave?

Best Regards,

Alexis Andalon 

[cerma]

Hi Alexis,

Code generated by ConfigTool:

void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)
{
assert(masterConfig);

/* Initializes the configure structure to zero. */
(void)memset(masterConfig, 0, sizeof(*masterConfig));

masterConfig->baudRate = 500000;
masterConfig->bitsPerFrame = 8;
masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh;
masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge;
masterConfig->direction = kLPSPI_MsbFirst;

masterConfig->pcsToSckDelayInNanoSec = 1000000000U / masterConfig->baudRate * 2U;
masterConfig->lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig->baudRate * 2U;
masterConfig->betweenTransferDelayInNanoSec = 1000000000U / masterConfig->baudRate * 2U;

masterConfig->whichPcs = kLPSPI_Pcs0;
masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow;

masterConfig->pinCfg = kLPSPI_SdiInSdoOut;
masterConfig->dataOutConfig = kLpspiDataOutRetained;
}

const lpspi_master_config_t LPSPI4_config = {
.baudRate = 10000000,
.bitsPerFrame = 16,
.cpol = kLPSPI_ClockPolarityActiveHigh,
.cpha = kLPSPI_ClockPhaseFirstEdge,
.direction = kLPSPI_MsbFirst,
.pcsToSckDelayInNanoSec = 0,
.lastSckToPcsDelayInNanoSec = 0,
.betweenTransferDelayInNanoSec = 0,
.whichPcs = kLPSPI_Pcs0,
.pcsActiveHighOrLow = kLPSPI_PcsActiveLow,
.pinCfg = kLPSPI_SdiInSdoOut,
.dataOutConfig = kLpspiDataOutTristate
};

I use a custom board(The Master device). The slave device is a pcb for display control. The display shows correctly. I just only don't understand the gap after the first word.

Best Regards,

Jaroslav

[Alexis_A]

Hello @cerma,

I'm wondering if the display is holding the lines to stop the communication until is ready to receive. Have you tried using other devices to check if this behavior is still the same?

Best Regards,

Alexis Andalon