SNVS LP battery fail detection

Sacha

I'm trying to get the recovery from power fail routines for my new application up and running and I am finding the SNVS LP documentation frustrating. Obviously, I need to know if the RTC value is valid before I decide to write a default value, and I look to the Digital Low-Voltage Detector for this purpose. (I.MX RT1160 reference manual, page 2020).

Configuring the reference value for LPLVDR is straightforward, but I am not happy about the references to the LP status register. According to the manual we should clear the low voltage event in this register after setting LPLVDR, yet there is no record of where this bit is in the register. Most bits are unidentified and marked as reserved. From what I can see, this situation is the same for other devices using the SNVS module.

Anyway, if we look into the SNVS_LP_Init() routine in the SDK, the implication is that the low voltage event is bit 8, as defined by SNVS_LPSR_LVD_MASK. But despite what the manual states it is set on initialisation, not cleared. And there is no function or macro to check for a valid state at power up, so what is it we are looking for to know if the battery has failed? Should it remain set after initialisation? Do I just ignore it and check LPLVDR directly?

I could just see how it seems to work, but I really need to understand how NXP intended it to work so I can make sure my application is reliable.

Regards.

Sacha.

EdwinHz

Hi @Sacha,

Please look for a better description of the SNVS registers under the Security Reference Manual, which can be downloaded here (the file is the same for both the RT1160 and RT1170):

That said, you will see the SRM states that this bit is 1 on reset, not cleared. After initialization, this bit is cleared with the SNVS_LPSR_LVD_MASK:

BR,
Edwin.

View solution in original post

EdwinHz

Hi @Sacha,

Please look for a better description of the SNVS registers under the Security Reference Manual, which can be downloaded here (the file is the same for both the RT1160 and RT1170):

That said, you will see the SRM states that this bit is 1 on reset, not cleared. After initialization, this bit is cleared with the SNVS_LPSR_LVD_MASK:

BR,
Edwin.

Sacha

Thanks Edwin,

I have requested access to this documentation.

To be fair to NXP, there is a note in the reference manual stating that information on security related bit fields is available in the security reference manual. I just don't see why the SNVS reset state bit would be classed as secure. Besides, it would still be nice to have a macro in the SDK to simply check this state.

Regards.

Sacha.

Sacha

Sorry. I meant bit 3, not bit 8. But my comments/ questions still stand.