SEMC clock setting

[Eugene3]

Hi

I'm designing an application using RT117x which has both SDRAM and FPGA(SRAM interface) on the same SEMC interface.
I'd like to configure like the following.
Is it possible to meet all of the following 3 requirements?
1. SDRAM clock(SEMC_CLK) = 166MHz
2. FPGA/SRAM clock (SEMC_CLKX0) = 60MHz
3. SEMC keeps output SRAM clock even when the SEMC accesses SDRAM.

As far as I confirmed, regarding 1&2, I could find the SDRAM clock frequency setting on Boot ROM XMCD, but I couldn't find SRAM clock frequency setting. Regarding 3, I think it's possible if I set IOCR[CLKX0_AO]=1b.

[Kan_Li · Accepted solution]

Hi @Eugene3 ,

It is possible to have both SDRAM and FPGA(SRAM interface) on the same SEMC interface, but not possible to drive different frequency on SEMC_CLK and SEMC_CLKX0 as only 1 SEMC module available on chip.

Hope that makes sense,

Have a great day,
Kan

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[Eugene3]

Hi Ken

Thank you for your replying.

I understand.

If I use SRAM as Asynchronous mode, is it possible to output same frequency from both of SEMC_CLK and SEMC_CLKX0, and continue to output SEMC_CLKX0 for SRAM even during SDRAM access period?

I'd like to use SEMC_CLKX0 for FPGA clock, but the Asynchronous mode timing is better for my application.

[Kan_Li]

Hi @Eugene3 ,

Yes, it is possible to have the same frequency from both of SEMC_CLK and SEMC_CLKX0, and continue to output SEMC_CLKX0 even during SDRAM access period.

Have a great day,
Kan

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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[Eugene3]

Thank you for your help.