product: I.mxrt 1170 series
For the SRAM write/read in SYNC mode (ADMUX), just wonder is it possible to mask the higher address bit, A[M : 16] and UB&LB, means not to use and free up my address pin, so that I can connect them to extra GPIOs?
My SRAM application only need A0-15. (which share together with D0-15)
Can the software call function/register support on masking or is the software/register adjustable? For masking the higher address bit, A[M : 16] and UB&LB, while using SRAM write/read in SYNC mode (ADMUX) . Thank you.
Or if we did not call the A[M : 16] and UB&LB, is it means we mask the features and free up those GPIOs?
