SEMC Configuration for SDRAM

[Pavankumar1]

Hi,

I am using a custom NXP RT1176 board, and in the SEMC interface for SDRAM, the hardware only provides address lines A0–A11. With this configuration, we can access a maximum of 16MB of SDRAM.

However, I would like to use 32MB, so I selected a 64MB SDRAM part (Alliance AS4C32M16SB) and left the A12 address line floating. My intention is to use the lower 32MB of the device.

I have configured SEMC for 64MB, mapping the memory range from 0x80000000 to 0x80FFFFFF. In this region, I am observing 16-bit read/write failures at certain addresses.

Interestingly, when I access memory from 0x81000000 to 0x81FFFFFF (the upper 32MB), it works correctly.

I’ve attached the code I used for configuration. Can you please review it and let me know if any improvements are needed, or if this kind of setup (with A12 floating) is valid and supported by SEMC?

Best regards,
Pavanakumar A G

[Omar_Anguiano]

Avoid floating  Lines. Ideally, do not leave A12 floating; tie it to a known logic level so you can access the lower half. 

BR,
Omar

[Pavankumar1]

Thank you, @Omar_Anguiano, for your reply.

On our board, A12 is floating on both the controller side and the SDRAM side. As you mentioned, A12 should be held at a known logic level. Could you please clarify:

What logic level should we use for A12 in this case (HIGH or LOW)?

Do we need to drive A12 to the same known level on both sides, or is it sufficient to set it only on the SDRAM side?

[Omar_Anguiano]

A12 should be held low on the SDRAM side(I suggest confirming this with the manufacturer). 

BR,
Omar