RTC_XTALI level for i.MX RT117x

[Ootsuka]

Hello teams.

I'm trying to desiged i.MX RT1171 custum board.

What is the maximum level of RTC_XTALI at logic level clock input?
Please tell me which is the correct answer.(I think it's VDD_SNVS_ANA level...)

In section 3.1 of the Datasheet, RTC_XTALI / RTC_XTALO is described up to the VDD_SNVS_DIG level.

Table 4. Special signal considerations
--------
"If you want to feed an external low-frequency clock into RTC_XTALI, the RTC_XTALO pin must
remain unconnected or driven by a complementary signal. The logic level of this forcing clock must
not exceed the VDD_SNVS_DIG level"

But, in section 4.2.6 of the Datasheet, RTC_XTALI is described up to the VDD_SNVS_ANA level.

Table 32. 32 kHz oscillator DC electrical specifications Note 3
--------
"The voltage of the applied clock must be within the range of VSS to VDD_SNVS_ANA."

VDD_SNVS_ANA=1.75V
VDD_SNVS_DIG=0.85V
And VDD_SNVS_DIG is not output by default.

Best regards.

[jeremyzhou · Accepted solution]

Hi，
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) What is the maximum level of RTC_XTALI at logic level clock input?
--In my opinion, I agree with your idea, it's VDD_SNVS_ANA level.
Have a great day,
TIC

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[Ootsuka]

Hello,

I am glad to inform you that the question is now solved.
I designed as VDD_SNVS_ANA level.

Thank you very much for answer.