RT685 i2s receives incorrect data in receive mode.

[Padi-2023]

Ask the masters：
I used two RT685 development boards for testing, one as the master mode as the transmitter, sending a regular data, and the other as the slave mode as the receiver, and found that the data received was not a regular data.

The following is the circuit diagram of the development board：

1、master  data-> slave data;

2、master  BLCK-> slave BLCK;

3、master  WS-> slave WS;

The following is the code from the pattern:

/********slave GPIO Config**********/

const uint32_t port0_pin7_config = (/* Pin is configured as FC1_SCK */
IOPCTL_PIO_FUNC1 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT0 PIN7 (coords: J2) is configured as FC1_SCK */
IOPCTL_PinMuxSet(IOPCTL, 0U, 7U, port0_pin7_config);

const uint32_t port0_pin8_config = (/* Pin is configured as FC1_TXD_SCL_MISO_WS */
IOPCTL_PIO_FUNC1 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT0 PIN8 (coords: K4) is configured as FC1_TXD_SCL_MISO_WS */
IOPCTL_PinMuxSet(IOPCTL, 0U, 8U, port0_pin8_config);

const uint32_t port0_pin9_config = (/* Pin is configured as FC1_RXD_SDA_MOSI_DATA */
IOPCTL_PIO_FUNC1 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT0 PIN9 (coords: L3) is configured as FC1_RXD_SDA_MOSI_DATA */
IOPCTL_PinMuxSet(IOPCTL, 0U, 9U, port0_pin9_config);

/********slave  I2S Config**********/

#define DEMO_I2S_RX (I2S1)
#define AUX_DMA (DMA0)
#define DEMO_I2S_RX_CHANNEL (2)
#define DEMO_I2S_RX_MODE kI2S_MasterSlaveNormalSlave 

/********slave I2S INIT()**********/

I2S_RxGetDefaultConfig(&s_RxConfig);
s_RxConfig.divider = DEMO_I2S_CLOCK_DIVIDER;
s_RxConfig.masterSlave = DEMO_I2S_RX_MODE;
s_RxConfig.frameLength = 64U;
I2S_RxInit(DEMO_I2S_RX, &s_RxConfig);
//AUX I2S RX data buff Config
s_RxTransfer.data = &s_Buffer[0];
s_RxTransfer.dataSize = sizeof(s_Buffer);
I2S_RxTransferCreateHandleDMA(DEMO_I2S_RX, &s_RxHandle, &s_DmaRxHandle, RxCallback, (void *)&s_RxTransfer);

I2S_RxTransferReceiveDMA(DEMO_I2S_RX, &s_RxHandle, s_RxTransfer);

/********master I2S INIT()**********/

DMA_EnableChannel(AMP_DMA, AMP_I2S_TX_CHANNEL);
DMA_SetChannelPriority(AMP_DMA,AMP_I2S_TX_CHANNEL, kDMA_ChannelPriority3);
DMA_CreateHandle(&s_AmpDmaTxHandle, AMP_DMA, AMP_I2S_TX_CHANNEL);

I2S_TxGetDefaultConfig(&s_AmpTxConfig);
s_AmpTxConfig.divider = AMP_I2S_CLOCK_DIVIDER;
s_AmpTxConfig.masterSlave = AMP_I2S_TX_MODE;
//s_AmpTxConfig.leftJust = true;
s_AmpTxConfig.frameLength = 64U;
//tx_config.oneChannel = true; //mono
I2S_TxInit(AMP_I2S_TX, &s_AmpTxConfig);

I2S_TxTransferCreateHandleDMA(AMP_I2S_TX, &s_AmpTxHandle, &s_AmpDmaTxHandle, AmpTxCallback, NULL);

The following screenshot is the data captured by the logic analyzer of the master mode:

The following screenshot captures the data from the mode's emulator:【slave】

[Omar_Anguiano]

Let me double check if  I understood the issue well. The receiver to I2S is showing incorrect data on the receiver buffer although the scope on the bus suggest that the data is sent correctly right? This may be an issue on the receiver buffer as the scope show correct data, please try moving the location of the receiving buffer and disable or invalidate cache before receiving.

Is your code based on the SDK examples?

Best regards,
Omar

[Padi-2023]

Is the routine modification, the current problem has been solved, is the DMA initialization problem again, but encountered another problem, is to use other I2S interface: Receiving with I2S3, i2s4 shares the WS and blck of I2S3, and now the signal value received by I2S3 is 0, but using the logic analyzer to grab the signal to see that the signal of the channel is available, and the value is non-0。

[Padi-2023]

Through experiments, it was found that if i2s3 shares i2s1's ws/bclk, i2s3 can successfully receive data; if I2S3 shares I2S4's ws/bclk, all the received data is 0.

[Padi-2023]

/********Mask the I2S clock from mode**********/

/* attach AUDIO PLL clock to FLEXCOMM1 (I2S1) */
// CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM1);
/* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */
CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3);

/* Set shared signal set 0: SCK, WS from Flexcomm1 */
// SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(1) | SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(1);
/* Set flexcomm3 SCK, WS from shared signal set 0 */
SYSCTL1->FCCTRLSEL[3] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) | SYSCTL1_FCCTRLSEL_WSINSEL(1);

[Padi-2023]

/********master  I2S Config**********/

#define AMP_AUDIO_SAMPLE_RATE (16000)

#define AMP_I2S_MASTER_CLOCK_FREQUENCY CLOCK_GetMclkClkFreq()
#define AMP_I2S_TX (I2S4)
#define AMP_DMA (DMA0)

#define AMP_I2S_TX_CHANNEL (9)

#define AMP_I2S_CLOCK_DIVIDER (24576000U / AMP_AUDIO_SAMPLE_RATE / 32U / 2)

#define AMP_I2S_TX_MODE kI2S_MasterSlaveNormalMaster