I'm running SAI3 in BCLK/SYNC slave mode and experience glitches which lead to sync errors, i.e. SEF interrupt (section 58.3.6.4). There seems to be no internal glitch filter on these clock inputs.
My question is: Does the RT1176 support input hysteresis?
Figure 13-3 and section 13.3.1.1.1 in the reference manual describe such a feature but I cannot find a way to enable that in the SW_PAD_CTL_xxx registers.
Hello, sorry for the late response, I was researching more information.
All IO support the hysteresis. and for datasheet, it only provide the input hysteresis value for GPIO_AD/GPIO_LPSR/GPIO_DISP_B2, and for GPIO_EMC_B2, it take the different IO lib, and the design don't provide the input hysteresis value in current datasheet, but it still support input hysteresis.
Thanks for your reply. I wasn't using RM Rev 2 for some reason, still had Rev 1.
This question remains: Which pins do actually support input hysteresis?
In the datasheet (IMXRT1170CEC, Rev. 4, 05/2023) I found an "Input Hysteresis" parameter in Table 37 which applies to GPIO_AD/GPIO_LPSR/GPIO_DISP_B2. However, I'm using GPIO_EMC_B2. This would be Table 35 which does not list such a parameter. So can I assume that GPIO_EMC_B2 pins do not implement hysteresis?
Hello, sorry for the late response, I was researching more information.
All IO support the hysteresis. and for datasheet, it only provide the input hysteresis value for GPIO_AD/GPIO_LPSR/GPIO_DISP_B2, and for GPIO_EMC_B2, it take the different IO lib, and the design don't provide the input hysteresis value in current datasheet, but it still support input hysteresis.
