RT1176 MIPI DSI VSYNC/HSYNC end command

[rhsalced]

Hello,

I’m working with the MIPI DSI interface on the RT1176 EVK. I was able to get the SD_JPEG example project up and running. I made some changes to the project since for my application the RT1176 will interface with an FPGA. 

The FPGA is successfully decoding the packets and receiving data. However, the FPGA receiver is expecting both the HSYNC/VSYNC start packets and HSYNC/VSYNC end packets, but the RT1176 is only sending the HSYNC and VSYNC start packets at the start of a line/frame. I’ve looked around the example project, but I can’t seem to find a way to enable the HSYNC/VSYNC end packets.

Is there a way to get the RT1176 to send the MIPI DSI HSYNC/VSYNC end packets?

Thanks,

Ricardo

[EdwinHz]

Hi @rhsalced,

I'm afraid that the MIPI DSI interface is not designed to generate HSYNC/VSYNC end packets, only start pulses, as stated on the following application note that goes into detail on how the MIPI DSI and CSI work on our devices: i.MX 8/RT MIPI DSI/CSI-2 (nxp.com)

I recommend you change the FPGA to only use starting pulses, if possible, to interface it with the i.MX RT1170.

BR,
Edwin.