RT1170 reset behavior

[stekre]

Can you provide a description of the different resets and reset behaviors for the RT1176 chip? I find different terms in the reference manual, but no description of these terms and what the difference is when starting up. This is the terms I have found and my understanding.

• Power On Reset
  • Will issue POR signal to all parts of the MCU and run the boot ROM
• Cold Reset
  • Will run boot ROM (but not issue POR)
• Warm Reset (SW reset)
  • Will NOT run boot ROM

[EdwinHz]

Hi @stekre,

> Do you mean that "global system reset" and "software configuration reset" do a cold reset according to my understanding - boot ROM run but POR is not issued?

Correct.

> Can I trust the data in RAM after any reset or will it be in an undefined state in some cases?

No. RAM data is undefined after a reset.

You wont find the definition of cold reset and warm reset on the RM. These terms are remnants from i.MX documentation. I will pass this insight forward to the documentation team in order for them to make the appropriate changes to the RM to provide better details about a cold and a warm reset.

BR,

Edwin.

[EdwinHz]

Hi @stekre,

Section "25.3.3 Reset Control" of the Reference Manual details the actual four situations which will cause a reset event, namely: Power-on reset (POR), Global system reset request, Software configuration and Low-power mode transaction), and the following sections show the behaviors for each. From this, we can see that the "Global system reset" would be a cold reset and "Software configuration" reset would be a cold reset.

BR,

Edwin.

[stekre]

Do you mean that "global system reset" and "software configuration reset" do a cold reset according to my understanding - boot ROM run but POR is not issued?

The term "cold reset" is used throughout the reference manual but I can't find any definition of this term and in Section "25.3.3 Reset Control" you don't mention or describe the term "cold reset".

The term "warm reset" is also used in section "78.2", "78.2.2" and "78.3.11", but I haven't found any description on how to issue a warm reset and what happens in such an event.

I need to know what parts of the system is reset and what is left untouched or undefined.
For instance; Can I trust the data in RAM after any reset or will it be in an undefined state in some cases?

The reason for my question is that we see that there is data in RAM after a watchdog timeout, even tough section "25.3.4 Reset behavior of the Power-on Reset" say that "all of the chip except SNVS is reset after POR" (we have set WDT bit so POR need to be issued to reset WDOG_B signal).