RT1170 SEMC multiplexing

[Eugene3]

I will connect SRAM and SDRAM on the same SEMC interface of my application board.

As far as I confirmed this question(https://community.nxp.com/t5/i-MX-RT/RT1170-SEMC-Async-SRAM-Question/m-p/1668609), I understand SEMC can interface with SRAM & SDRAM in the same design.

But how can I switch the role of co-exist pins between SRAM access and SDRAM access? 

[Kan_Li]

Hi @Eugene3 ,

For data and address lines, no problem from sharing with each other, but please note the control lines especially the CS signal should be used by one device only.

Have a great day,
Kan

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[Eugene3]

Hi @Kan_Li 

Thank you, I'll share data and address lines, and I'll initialize SDRAMCRn and SRAMCRn.
But the role of these lines will be switching dinamatically while RT1170 is running, since the line has multiple roles.
How is dinamic change of line roles controlled?

For example, regarding GPIO_EMC_B2_00,
it is used as data16 during accessing to SDRAM　area, and it's used as address8 during accessing to SRAM.
Will CPU automatically switch these roles depending on the accessed address area?

If yes, when will the SEMC switch the line role? Is it the same clock timing of CS change?

[Kan_Li · Accepted solution]

Hi @Eugene3 ,

Most of the SEMC pins are controlled by hardware, which means the SEMC determines the pin
function according to its internal state, what you have to configure is the pin function controlled by IOCR, which should be static configured. Dynamic remapping of pin muxing controlled by IOCR is not supported.

Hope that makes sense ,

Have a great day,
Kan

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[Eugene3]

Hi @Kan_Li 

Thank you, I understand.